Freescale Semiconductor MPC8260 - Manual (Page 63)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor lxi
Figures
Figure
Number
Title
Page
Number
36-9 FCC Status Register (FCCS)............................................................................................... 36-16
37-1 In-Line Synchronization Pattern ........................................................................................... 37-2
37-2 Sending Transparent Frames between PowerQUICC IIs...................................................... 37-4
38-1 SPI Block Diagram ............................................................................................................... 38-1
38-2 Single-Master/Multi-Slave Configuration ............................................................................ 38-3
38-3 Multimaster Configuration.................................................................................................... 38-5
38-4 SPMODE—SPI Mode Register ............................................................................................ 38-6
38-5 SPI Transfer Format with SPMODE[CP] = 0....................................................................... 38-7
38-6 SPI Transfer Format with SPMODE[CP] = 1....................................................................... 38-8
38-7 SPIE/SPIM—SPI Event/Mask Registers .............................................................................. 38-9
38-8 SPCOM—SPI Command Register ..................................................................................... 38-10
38-9 RFCR/TFCR—Function Code Registers............................................................................ 38-12
38-10 SPI Memory Structure......................................................................................................... 38-13
38-11 SPI RxBD............................................................................................................................ 38-14
38-12 SPI TxBD ............................................................................................................................ 38-15
39-1 I
2
C Controller Block Diagram .............................................................................................. 39-1
39-2 I
2
C Master/Slave General Configuration.............................................................................. 39-2
39-3 I
2
C Transfer Timing .............................................................................................................. 39-3
39-4 I
2
C Master Write Timing ...................................................................................................... 39-3
39-5 I
2
C Master Read Timing ....................................................................................................... 39-4
39-6 I
2
C Mode Register (I2MOD) ................................................................................................ 39-6
39-7 I
2
C Address Register (I2ADD) ............................................................................................. 39-7
39-8 I
2
C Baud Rate Generator Register (I2BRG)......................................................................... 39-7
39-9 I2C Event/Mask Registers (I2CER/I2CMR) ........................................................................ 39-8
39-10 I
2
C Command Register (I2COM) ......................................................................................... 39-8
39-11 I
2
C Function Code Registers (RFCR/TFCR)..................................................................... 39-10
39-12 I
2
C Memory Structure......................................................................................................... 39-12
39-13 I
2
C RxBD............................................................................................................................ 39-13
39-14 I
2
C TxBD ............................................................................................................................ 39-14
40-1 Port Open-Drain Registers (PODRA–PODRD) ................................................................... 40-2
40-2 Port Data Registers (PDATA–PDATD) ................................................................................ 40-3
40-3 Port Data Direction Register (PDIR) .................................................................................... 40-3
40-4 Port Pin Assignment Register (PPARA–PPARD)................................................................. 40-4
40-5 Special Options Registers (PSORA–POSRD) ...................................................................... 40-5
40-6 Port Functional Operation ..................................................................................................... 40-6
40-7 Primary and Secondary Option Programming ...................................................................... 40-8