Freescale Semiconductor MPC8260 - Manual (Page 602)

Serial Interface with Time-Slot Assigner
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
15-26 Freescale Semiconductor
(physical layer device) and has separate receive and transmit sections. Although the PowerQUICC II has
eight TDMs, it can support only four independent IDL buses (limited by the number of serials that support
IDL) using separate clocks and sync pulses.
Figure 15-21 shows an application with two IDL buses.
Figure 15-21. Dual IDL Bus Application Example
15.6.1 IDL Interface Example
An example of the IDL application is the ISDN terminal adaptor shown in Figure 15-22.. In such an
application, the IDL interface is used to connect the 2B+D channels between the PowerQUICC II,
CODEC, and S/T transceiver. One of the PowerQUICC II’s SCCs is configured to HDLC mode to handle
the D channel; another PowerQUICC II’s SCC is used to rate adapt the terminal data stream over the first
B channel. That SCC is configured for HDLC mode if V.120 rate adaptation is required. The second B
channel is then routed to the CODEC as a digital voice channel, if preferred. The SPI is used to send
initialization commands and periodically check status from the S/T transceiver. The SMC connected to the
terminal is configured for UART.
PowerQUICC II
S/T
S/T
U
U
S/T
S/T
IDL1
S/T
Interfaces
IDL2
ISDN TE NT
U
Interfaces