Table 23-13. scce/sccm field descriptions, 15 scc status registers (sccs), Figure 23-9. scc status registers (sccs) – Freescale Semiconductor MPC8260 User Manual
Page 766: Scc status registers (sccs) -16, Scce/sccm field descriptions -16, Table 23-13 des cribes scce and sccm fields
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SCC BISYNC Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
23-16
Freescale Semiconductor
describes SCCE and SCCM fields.
23.15 SCC Status Registers (SCCS)
The SCC status (SCCS) register, seen in
, allows real-time monitoring of RXD. The real-time
status of CTS and CD are part of the parallel I/O.
describes SCCS fields.
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
—
DCC
—
GRA
—
TXE
RCH
BSY
TXB
RXB
Reset
0000_0000_0000_0000
R/W
R/W
Addr
0x0x11A10 (SCCE1); 0x0x11A30 (SCCE2); 0x0x11A50 (SCCE3); 0x0x11A70 (SCCE4)
0x0x11A14 (SCCM1); 0x0x11A34 (SCCM2); 0x0x11A54 (SCCM3); 0x0x11A74 (SCCM4)
Figure 23-8. BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)
Table 23-13. SCCE/SCCM Field Descriptions
1
1
Reserved bits in the SCCE should not be masked in the SCCM register.
Bits
Name
Description
0–4
—
Reserved, should be cleared. Refer to note 1 below.
5
DCC
DPLL CS changed. Set when carrier sense status generated by the DPLL changes. Real-time
status can be found in SCCS. This is not the CD status discussed elsewhere. Valid only when DPLL
is used.
6–7
—
Reserved, should be cleared. Refer to note 1 below.
8
GRA
Graceful stop complete. Set as soon the transmitter finishes any message in progress when a
GRACEFUL
STOP
TRANSMIT
is issued (immediately if no message is in progress).
9–10
—
Reserved, should be cleared. Refer to note 1 below.
11
TXE
Tx Error. Set when an error occurs on the transmitter channel.
12
RCH
Receive character. Set when a character is received and written to the buffer.
13
BSY
Busy. Set when a character is received and discarded due to a lack of buffers. The receiver resumes
reception after an
ENTER
HUNT
MODE
command.
14
TXB
Tx buffer. Set when a buffer is sent. TXB is set as the last bit of data or the BCS begins transmission.
15
RXB
Rx buffer. Set when the CPM closes the receive buffer on the BISYNC channel.
0
5
6
7
Field
—
CS
—
Reset
0000_0000
R/W
R
Addr
0x0x11A17 (SCCS1); 0x0x11A37 (SCCS2); 0x0x11A57 (SCCS3); 0x0x11A77 (SCCS4)
Figure 23-9. SCC Status Registers (SCCS)