Freescale Semiconductor MPC8260 - Manual (Page 1345)

Index P–P
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor Index-17
inbound door bell machine check, 9-100
inbound post queue overflow, 9-100
outbound free queue overflow, 9-100
illegal register access error, 9-98
PCI bus error signals, 9-97
error reporting, 9-98
parity error (PERR), 9-98
system error (SERR), 9-98
PCI interface, 9-98
address parity error, 9-99
data parity error, 9-99
master-abort transaction termination, 9-99
nmi, 9-100
target-abort error, 9-100
in PowerQUICC II, 9-2
initialization, 9-3
interface, 9-5
bus arbitration, 9-19
alogrithm, 9-19
master latency timer, 9-20
parking, 9-19
operation, 9-6
bus commands, 9-6
bus transactions
read and write, 9-9
termination, 9-11
error functions, 9-17
parity, 9-17
reporting, 9-18
other bus operations, 9-13
agent mode configuration access, 9-16
data streaming, 9-14
device selection, 9-13
fast back-to-back transactions, 9-14
host mode configuration access, 9-15
interrupt acknowledge, 9-17
special cycle command, 9-16
protocol fundamentals, 9-7
addressing, 9-8
basic transfer control, 9-8
bus driving and turnaround, 9-9
byte enable signals, 9-9
interrupts from, 9-4
message unit (I2O), 9-65
door bell registers, 9-67
inbound (IDR), 9-68
outbound (ODR), 9-67
I20 unit, 9-69
I20 registers, 9-77
inbound FIFO queue port register (IFQPR), 9-77
inbound message interrupt mask register (IMIMR),
9-82
inbound message interrupt status register (IMISR),
9-80
messaging unit control register (MUCR), 9-83
outbound FIFO queue port register (OFQPR), 9-78
outbound message interrupt mask register
(OMIMR), 9-79
outbound message interrupt status register
(OMISR), 9-78
queue base address register (QBAR), 9-84
inbound FIFOs, 9-70
PCI configuration identification, 9-70
inbound FIFOs
Free_FIFO head pointer register (IFHPR), 9-71
Free_FIFO tail pointer register (IFTPR), 9-71
post_FIFO head pointer register (IPHPR), 9-72
post_FIFO tail pointer register (IPTPR), 9-72
message registers, 9-65
inbound message registers (IMRx), 9-66
outbound message registers (OMRx), 9-66
outbound FIFOs, 9-74
free_FIFO head pointer register (OFHPR), 9-74
free_FIFO tail pointer register (OFTPR), 9-74
post_FIFO head pointer register (OPHPR), 9-75
post_FIFO head pointer register (OPTPR), 9-75
PCI parity operation, 9-18
SDMA interface, 9-3
signals, 9-3
single beat read example, 9-10
single beat write example, 9-11
structure, 9-2
target-initiated terminations, 9-12
PDATx (port data) registers, 40-2
PDIRx (port data direction registers), 40-3
PDTEA (SDMA 60x bus transfer error address register), 19-4
PDTEM (SDMA 60x bus transfer error MSNUM register),
19-4
PISCR (periodic interrupt status and control register), 4-46
PITC (periodic interrupt timer count register), 4-46
PITR (periodic interrupt timer register), 4-47
PODRx (port open-drain registers), 40-1
PORESET,, 6-14
Power consumption
FCCs, 29-22
SCCs, 20-25
PPAR (port pin assignment register), 40-4
PPC_ACR (60x bus arbiter configuration register), 4-29
PPC_ALRH (60x bus arbitration high-level register), 4-30
PPC_ALRL (60x bus arbitration low-level register), 4-31
Programming examples
serial communications controllers (SCCs)
GSMR (general SCC mode register)
AppleTalk mode, 26-3