Freescale Semiconductor MPC8260 - Manual (Page 263)

60x Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 7-7
State Meaning Asserted—Indicates that another device has begun a bus transaction and that the
address bus and transfer attribute signals are valid for snooping and in slave mode.
Negated—Has no special meaning.
Timing Comments Assertion/Negation—Must be valid on the same cycle that TS is asserted; sampled
by the processor only on this cycle.
7.2.4 Address Transfer Attribute Signals
In internal only mode the address transfer attribute signals have no meaning.
The transfer attribute signals are a set of signals that further characterize the transfer—such as the size of
the transfer, whether it is a read or write operation, and whether it is a burst or single-beat transfer. For a
detailed description of how these signals interact, see
Section 7.2.4, “Address Transfer Attribute Signals.”
7.2.4.1 Transfer Type (TT[0–4])
The transfer type signals (TT[0–4]) consist of five input/output signals on the PowerQUICC II. For a
complete description of TT[0–4] signals and transfer type encoding, see
Section 8.4.3.1, “Transfer Type
Signal (TT[0–4]) Encoding.”
7.2.4.1.1 Transfer Type (TT[0–4])—Output
Following are the state meaning and timing comments for the TT[0–4] output signals on the PowerQUICC
II.
State Meaning Asserted/Negated—Specifies the type of transfer in progress.
Timing Comments Assertion/Negation—Same as A[0–31].
High Impedance—Same as A[0–31].
7.2.4.1.2 Transfer Type (TT[0–4])—Input
Following are the state meaning and timing comments for the TT[0–4] input signals on the PowerQUICC
II.
State Meaning Asserted/Negated—Specifies the type of transfer in progress for snooping by the
PowerQUICC II.
Timing Comments Assertion/Negation—Same as A[0–31].
7.2.4.2 Transfer Size (TSIZ[0–3])
The transfer size (TSIZ[0–3]) signals consist of four input/output signals on the PowerQUICC II,
following are the state meaning and timing comments for the TSIZ[0–3] signals on the PowerQUICC II.
State Meaning Asserted/Negated—Specifies the data transfer size for the transaction (see
Section 8.4.3.3, “TBST and TSIZ[0–3] Signals and Size of Transfer” ). During
graphics transfer operations, these signals form part of the Resource ID (see
TBST).
Timing Comments Assertion/Negation—Same as A[0–31].