2 pci bridge configuration registers, Pci bridge configuration registers -45, Pci bridge pci configuration registers -45 – Freescale Semiconductor MPC8260 User Manual

Page 351: Pci bridge configuration registers

PCI Bridge

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

Freescale Semiconductor

9-45

9.11.2

PCI Bridge Configuration Registers

The PCI Local Bus Specification defines the configuration registers from 0x00 through 0x3F. Additionally,
the PCI bridge specifies these additional registers: the PCI function register (at offset 0x44), the PCI arbiter
control register (at offset 0x46), and the PCI Hot Swap register block (at offset 0x48).

Table 9-19

and

Figure 9-32

shows the PCI configuration registers provided by the PCI bridge for the PCI bus.

Note the following sections that apply to all PCI configuration registers (they appear immediately after the
descriptions of individual registers):

•

Section 9.11.2.26, “PCI Configuration Register Access from the Core,” on page 9-62

•

Section 9.11.2.27, “PCI Configuration Register Access in Big-Endian Mode,” on page 9-62

•

Section 9.11.2.28, “Initializing the PCI Configuration Registers,” on page 9-64

Table 9-19. PCI Bridge PCI Configuration Registers