Freescale Semiconductor MPC8260 - Manual (Page 1303)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor B-1
Appendix B
Reference Manual (Rev 1) Errata
This appendix lists errata to revision 1 of the MPC8260 PowerQUICC II™ User’s Manual. It is intended
solely as a quick reference for users who are familiar with revision 1. These errata have been incorporated
into the current manual. Therefore, the following information is redundant.
This appendix contains the last published version of the errata document (rev 2.1, 04/2004).
NOTE
All numbering corresponds to revision 1 of the MPC8260 PowerQUICC
II™ User’s Manual. This includes section and page numbers of each
erratum (provided on the left-hand margin) as well as table and figure
numbers.
B.1 Document Errata
The following list includes the document errata:
Section/Page Changes
4.3.1.1, 4-19 In Table 4-4, the reserved field should be bits 8–13 (as shown in Figure 4-10) and
not 8–14. Bit 14 is GSIU (group SIU).
4.3.1.3, 4-21 In Table 4-6, descriptions for bits 3–31 should appear as follows:
4.3.1.3, 4-22 In Table 4-7, descriptions for bits 3–31 should appear as follows:
4.3.2.1, 4-28 In Figure 4-21, the note on reset (“Depends on reset configuration sequence...”)
should only apply to bits 0 and 27 [EBM, ISPS]. All other BCR bits are cleared at
reset.
3–11 XC2P–XC4P Same as XC1P, but for XCC2–XCC4
12–15 — Reserved, should be cleared.
16–27 XC5P–XC8P Same as XC1P, but for XCC5–XCC8
28–31 — Reserved, should be cleared.
3–11 YC2P–YC8P Same as YC1P, but for YCC2–YCC8
12–15 — Reserved, should be cleared.
16–27 YC5P–YC8P Same as YC1P, but for YCC5–YCC8
28–31 — Reserved, should be cleared.