Freescale Semiconductor MPC8260 - Manual (Page 11)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor ix
Contents
Paragraph
Number
Title
Page
Number
5.4.2.2 Single PowerQUICC II Configured from Boot EPROM ...................................... 5-10
5.4.2.3 Multiple PowerQUICC IIs Configured from Boot EPROM ................................. 5-11
5.4.2.4 Multiple PowerQUICC IIs in a System with No EPROM .................................... 5-13
Chapter 6
External Signals
6.1 Functional Pinout ............................................................................................................. 6-1
6.2 Signal Descriptions .......................................................................................................... 6-2
Chapter 7
60x Signals
7.1 Signal Configuration........................................................................................................ 7-2
7.2 Signal Descriptions .......................................................................................................... 7-2
7.2.1 Address Bus Arbitration Signals.................................................................................. 7-3
7.2.1.1 Bus Request (BR)—Output ..................................................................................... 7-3
7.2.1.1.1 Address Bus Request (BR)—Output ................................................................... 7-3
7.2.1.1.2 Address Bus Request (BR)—Input...................................................................... 7-3
7.2.1.2 Bus Grant (BG)........................................................................................................ 7-4
7.2.1.2.1 Bus Grant (BG)—Input ....................................................................................... 7-4
7.2.1.2.2 Bus Grant (BG)—Output..................................................................................... 7-4
7.2.1.3 Address Bus Busy (ABB)........................................................................................ 7-5
7.2.1.3.1 Address Bus Busy (ABB)—Output..................................................................... 7-5
7.2.1.3.2 Address Bus Busy (ABB)—Input ....................................................................... 7-5
7.2.2 Address Transfer Start Signal ...................................................................................... 7-5
7.2.2.1 Transfer Start (TS) ................................................................................................... 7-5
7.2.2.1.1 Transfer Start (TS)—Output ................................................................................ 7-5
7.2.2.2 Transfer Start (TS)—Input....................................................................................... 7-6
7.2.3 Address Transfer Signals ............................................................................................. 7-6
7.2.3.1 Address Bus (A[0–31])............................................................................................ 7-6
7.2.3.1.1 Address Bus (A[0–31])—Output......................................................................... 7-6
7.2.3.1.2 Address Bus (A[0–31])—Input ........................................................................... 7-6
7.2.4 Address Transfer Attribute Signals.............................................................................. 7-7
7.2.4.1 Transfer Type (TT[0–4]).......................................................................................... 7-7
7.2.4.1.1 Transfer Type (TT[0–4])—Output....................................................................... 7-7
7.2.4.1.2 Transfer Type (TT[0–4])—Input ......................................................................... 7-7
7.2.4.2 Transfer Size (TSIZ[0–3]) ....................................................................................... 7-7
7.2.4.3 Transfer Burst (TBST)............................................................................................. 7-8
7.2.4.4 Global (GBL)........................................................................................................... 7-8
7.2.4.4.1 Global (GBL)—Output........................................................................................ 7-8