Freescale Semiconductor MPC8260 - Manual (Page 438)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-20 Freescale Semiconductor
11.3.3 60x SDRAM Mode Register (PSDMR)
The 60x SDRAM mode register (PSDMR), shown in Figure 11-10 , is used to configure operations
pertaining to SDRAM.
Table 11-8 describes PSDMR fields. LSMDR fields are described in Table 11-9..
23 BI Burst inhibit. Indicates if this memory bank supports burst accesses.
0 The bank supports burst accesses
1 The bank does not support burst accesses. The UPMx executes burst accesses as series of
single accesses.
24–28 — Reserved, should be cleared.
29–30 EHTR Extended hold time on read accesses. Indicates how many cycles are inserted between a read
access from the current bank and the next access.
00 Normal timing is generated by the memory controller. No additional cycles are inserted.
01 One idle clock cycle is inserted.
10 Four idle clock cycles are inserted.
11 Eight idle clock cycles are inserted.
31 — Reserved, should be cleared.
0 1 2 4 5 7 8 11 13 14 15
Field PBI RFEN OP SDAM BSMA SDA10 RFRC
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x0x10190 (PSDMR), 0x0x10194 (LSDMR)
16 17 19 20 22 23 24 25 26 27 28 29 30 31
Field RFRC PRETOACT ACTTORW BL LDOTOPRE WRC EAMUX BUFCMD
CL
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10192 (PSDMR), 0x10196 (LSDMR)
Figure 11-10. 60x/Local SDRAM Mode Register (PSDMR/LSDMR)
Table 11-7. Option Register (OR x)—UPM Mode
Bits Name Description