Freescale Semiconductor MPC8260 - Manual (Page 1199)

Fast Ethernet Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 35-3
• Performs framing functions
— Preamble generation and stripping
— Destination address checking
— CRC generation and checking
— Automatic padding of short frames on transmit
— Framing error (dribbling bits) handling
• Full collision support
— Enforces the collision (jamming and TX_ER assertion)
— Truncated binary exponential backoff algorithm for random wait
— Two nonaggressive backoff modes
— Automatic frame retransmission (until retry limit is reached)
— Automatic discard of incoming collided frames
— Delay transmission of new frames for specified interframe gap
• Bit rates up to 100 Mbps
• Receives back-to-back frames
• Detection of receive frames that are too long
• Multibuffer data structure
• Supports 48-bit addresses in three modes
— Physical. One 48-bit address recognized or 64-bin hash table for physical addresses
— Logical. 64-bin group address hash table plus broadcast address checking
— Promiscuous. Receives all frames regardless of address (a CAM can be used for address
filtering)
• External CAM support on system bus interfaces
• Special RMON counters for monitoring network statistics
• Transmitter network management and diagnostics
— Lost carrier sense
— Underrun
— Number of collisions exceeded the maximum allowed
— Number of retries per frame
— Deferred frame indication
— Late collision
• Receiver network management and diagnostics
— CRC error indication
— Nonoctet alignment error
— Frame too short
— Frame too long
— Overrun