Freescale Semiconductor MPC8260 - Manual (Page 211)

System Interface Unit (SIU)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 4-39
Table 4-15 describes TESCR1 fields.
0 1 2 3 4 5 6 7 9 10 11 15
Field BM ISBE PAR ECC2 ECC1 WP EXT TC — TT
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x0x10040
16 17 18 19 20 21 22 23 24 31
Field — DMD — PCIMCP
1
DER
2
IRQ0
2
SWD
2
ADO
2
ECNT
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10042
1 MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices.
2
Reserved on .29
µm (HiP3) Rev A.1 devices.
Note: Bits 0–15 and 19–23 are status bits and are cleared by writing 1s.
Figure 4-31. 60x Bus Transfer Error Status and Control Register 1 (TESCR1)
Table 4-15. TESCR1 Field Descriptions
Bits Name Description
0 BM 60x bus monitor time-out. Set when TEA is asserted due to the 60x bus monitor time-out.
1 ISBE Internal space bus error. Indicates that one of the following occurred:
• TEA was asserted due to an error on a transaction to PowerQUICC II’s internal memory space
• An MCP was caused by a parity error on a transaction to PowerQUICC II’s internal memory
space. Possible only if BCR[SPAR] = 1(.25 µm (HiP4) devices only) .
TESCR2[REGS,DPR, LCL, PCI0, PCI1] indicate which of PowerQUICC II’s internal slaves caused
the error. TESCR2[PCI0, PCI1] are only on the MPC8250, the MPC8265, and the MPC8266.
2 PAR 60x bus parity error. Indicates that an MCP was caused due to one of the following:
• Parity error on 60x bus access controlled by the memory controller. TESCR2[PB] indicates which
byte lane caused the error; TESCR2[BNK] indicates which memory controller bank was
accessed.
• Parity error on a transaction to PowerQUICC II’s internal memory space. Possible only if
BCR[SPAR] = 1 (.25 µm (HiP4) devices only).
3 ECC2 Double ECC error. Indicates that MCP was asserted due to double ECC error on the 60x bus.
TESCR2[BNK] indicates which memory controller bank was accessed.
4 ECC1 Single ECC error. Indicates that MCP was asserted due to single bit ECC error on the 60x bus.
TESCR2[BNK] indicates which memory controller bank was accessed. Single-bit errors are fixed
by the ECC logic. However, if the ECC counter (ECNT) has reached its maximum value, all single-bit
errors cause the assertion of MCP.
5 WP Write protect error. Indicates that a write was attempted to a 60x bus memory region that was
defined as read-only in the memory controller. Note that this alone does not cause TEA assertion.
Usually, in this case, the bus monitor will time-out.
6 EXT External error. Indicates that TEA was asserted by an external bus slave.