Freescale Semiconductor MPC8260 - Manual (Page 725)

SCC UART Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 21-21
21.20 SCC UART Status Register (SCCS)
The SCC UART status register (SCCS), shown in Figure 21-12 , monitors the real-time status of RXD.
Table 21-13 describes UART SCCS fields.
Table 21-12. SCCE/SCCM Field Descriptions for UART Mode
1
1
Reserved bits in the SCCE should not be masked in the SCCM register.
Bit Name Description
0–5 — Reserved, should be cleared. Refer to note 1 below.
6 AB Autobaud. Set when an autobaud lock is detected. The core should rewrite the baud rate generator
with the precise divider value. See
Chapter 17, “Baud-Rate Generators (BRGs) .”
7 IDL Idle sequence status changed. Set when the channel detects a change in the serial line. The line’s
real-time status can be read in SCCS[ID]. Idle is entered when a character of all ones is received; it
is exited when a zero is received.
8 GRA Graceful stop complete. Set as soon as the transmitter finishes any buffer in progress after a
GRACEFUL STOP TRANSMIT command is issued. It is set immediately if no buffer is in progress.
9 BRKE Break end. Set when an idle bit is received after a break sequence.
10 BRKS Break start. Set when the first character of a break sequence is received. Multiple BRKS events are
not received if a long break sequence is received.
11 — Reserved, should be cleared. Refer to note 1 below.
12 CCR Control character received and rejected. Set when a control character is recognized and stored in
the receive control character register RCCR.
13 BSY Busy. Set when a character is received and discarded due to a lack of buffers. In multidrop mode,
the receiver automatically enters hunt mode; otherwise, reception continues when a buffer is
available. The latest point that an RxBD can be changed to empty and guarantee avoiding the busy
condition is the middle of the stop bit of the first character to be stored in that buffer.
14 TX Tx event. Set when a buffer is sent. If TxBD[CR] = 1, TX is set no sooner than when the last stop bit
of the last character in the buffer begins transmission. If TxBD[CR] = 0, TX is set after the last
character is written to the Tx FIFO. TX also represents a CTS lost error; check TxBD[CT].
15 RX Rx event. Set when a buffer is received, which is no sooner than the middle of the first stop bit of the
character that caused the buffer to close. Also represents a general receiver error (overrun, CD lost,
parity, idle sequence, and framing errors); the RxBD status and control fields indicate the specific
error.
0 6 7
Field — ID
Reset 0000_0000_0000_0000
R/W R
Addr 0x0x11A17 (SCCS1); 0x0x11A37 (SCCS2); 0x0x11A57 (SCCS3); 0x0x11A77 (SCCS4)
Figure 21-12. SCC Status Register for UART Mode (SCCS)