Freescale Semiconductor MPC8260 - Manual (Page 31)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor xxix
Contents
Paragraph
Number
Title
Page
Number
28.3.4.3 SS7 Configuration Register—SS7 Mode ............................................................ 28-24
28.3.4.3.1 AERM Implementation ................................................................................... 28-25
28.3.4.3.2 AERM in Japanese SS7 ................................................................................... 28-25
28.3.4.3.3 Disabling SUERM ........................................................................................... 28-26
28.3.4.4 SU Filtering—SS7 Mode..................................................................................... 28-26
28.3.4.4.1 Comparison Mask............................................................................................ 28-26
28.3.4.4.2 Comparison State Machine.............................................................................. 28-26
28.3.4.4.3 Filtering Limitations ........................................................................................ 28-27
28.3.4.4.4 Resetting the SU Filtering Mechanism............................................................ 28-27
28.3.4.5 Octet Counting Mode—SS7 Mode...................................................................... 28-28
28.4 Channel Extra Parameters............................................................................................ 28-28
28.5 Superchannels .............................................................................................................. 28-29
28.5.1 Superchannel Table.................................................................................................. 28-29
28.5.2 Superchannels and Receiving .................................................................................. 28-30
28.5.3 Transparent Slot Synchronization............................................................................ 28-30
28.5.4 Superchannelling Programming Examples.............................................................. 28-30
28.6 MCC Configuration Registers (MCCFx) .................................................................... 28-33
28.7 MCC Commands ......................................................................................................... 28-34
28.8 MCC Exceptions .......................................................................................................... 28-35
28.8.1 MCC Event Register (MCCE)/Mask Register (MCCM) ........................................ 28-37
28.8.1.1 Interrupt Circular Table Entry ............................................................................. 28-38
28.8.1.2 Global Transmitter Underrun (GUN) .................................................................. 28-40
28.8.1.2.1 TDM Clock...................................................................................................... 28-40
28.8.1.2.2 Synchronization Pulse ..................................................................................... 28-40
28.8.1.2.3 SIRAM Programming...................................................................................... 28-41
28.8.1.2.4 MCC Initialization ........................................................................................... 28-41
28.8.1.2.5 CPM Bandwidth .............................................................................................. 28-41
28.8.1.2.6 CPM Priority.................................................................................................... 28-42
28.8.1.2.7 Bus Latency ..................................................................................................... 28-42
28.8.1.3 Recovery from GUN Errors................................................................................. 28-42
28.8.1.4 Global Overrun (GOV)........................................................................................ 28-43
28.9 MCC Buffer Descriptors.............................................................................................. 28-43
28.9.1 Receive Buffer Descriptor (RxBD) ......................................................................... 28-43
28.9.2 Transmit Buffer Descriptor (TxBD) ........................................................................ 28-45
28.10 MCC Initialization and Start/Stop Sequence ............................................................... 28-47
28.10.1 Stopping and Restarting a Single-Channel .............................................................. 28-48
28.10.2 Stopping and Restarting a Superchannel ................................................................. 28-49
28.11 MCC Latency and Performance .................................................................................. 28-49