Freescale Semiconductor MPC8260 Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for MPC8260 Freescale Semiconductor
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| Recognized languages: | English |
|---|---|
| Pages: | 1360 |
| Size: | 9.52 MB |
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Document Outline
- MPC8260 PowerQUICC™ II Family Reference Manual
- About This Book
- Part I Overview
- Chapter 1 Overview
- 1.1 Features
- 1.2 Architecture Overview
- 1.3 Software Compatibility Issues
- 1.4 Differences between MPC860 and PowerQUICC II
- 1.5 Serial Protocol Table
- 1.6 PowerQUICC II Configurations
- 1.7 Application Examples
- 1.7.1 Communication Systems
- 1.7.2 Bus Configurations
- Chapter 2 G2 Core
- 2.1 Overview
- 2.2 G2 Processor Core Features
- 2.3 Programming Model
- 2.3.1 Register Set
- 2.3.2 PowerPC Instruction Set and Addressing Modes
- 2.4 Cache Implementation
- 2.5 Exception Model
- 2.6 Memory Management
- 2.7 Instruction Timing
- 2.8 Differences between the PowerQUICC II’s G2 Core and the MPC603e Microprocessor
- Chapter 3 Memory Map
- Part II Configuration and Reset
- Chapter 4 System Interface Unit (SIU)
- Figure 4-1. SIU Block Diagram
- 4.1 System Configuration and Protection
- 4.2 Interrupt Controller
- 4.3 Programming Model
- 4.3.1 Interrupt Controller Registers
- 4.3.1.1 SIU Interrupt Configuration Register (SICR)
- 4.3.1.2 SIU Interrupt Priority Register (SIPRR)
- 4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)
- 4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)
- 4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L)
- 4.3.1.6 SIU Interrupt Vector Register (SIVEC)
- 4.3.1.7 SIU External Interrupt Control Register (SIEXR)
- 4.3.2 System Configuration and Protection Registers
- 4.3.2.1 Bus Configuration Register (BCR)
- 4.3.2.2 60x Bus Arbiter Configuration Register (PPC_ACR)
- 4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)
- 4.3.2.4 Local Bus Arbiter Configuration Register (LCL_ACR)
- 4.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL)
- 4.3.2.6 SIU Module Configuration Register (SIUMCR)
- 4.3.2.7 Internal Memory Map Register (IMMR)
- 4.3.2.8 System Protection Control Register (SYPCR)
- 4.3.2.9 Software Service Register (SWSR)
- 4.3.2.10 60x Bus Transfer Error Status and Control Register 1 (TESCR1)
- 4.3.2.11 60x Bus Transfer Error Status and Control Register 2 (TESCR2)
- 4.3.2.12 Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)
- 4.3.2.13 Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)
- 4.3.2.14 Time Counter Status and Control Register (TMCNTSC)
- 4.3.2.15 Time Counter Register (TMCNT)
- 4.3.2.16 Time Counter Alarm Register (TMCNTAL)
- 4.3.3 Periodic Interrupt Registers
- 4.3.4 PCI Control Registers
- 4.3.1 Interrupt Controller Registers
- 4.4 SIU Pin Multiplexing
- Chapter 5 Reset
- 5.1 Reset Causes
- 5.2 Reset Status Register (RSR)
- 5.3 Reset Mode Register (RMR)
- 5.4 Reset Configuration
- Table 5-5. RSTCONF Connections in Multiple-PowerQUICC II Systems (continued)
- Table 5-6. Configuration EPROM Addresses
- 5.4.1 Hard Reset Configuration Word
- 5.4.2 Hard Reset Configuration Examples
- Part III The Hardware Interface
- Chapter 6 External Signals
- Chapter 7 60x Signals
- 7.1 Signal Configuration
- 7.2 Signal Descriptions
- 7.2.1 Address Bus Arbitration Signals
- 7.2.2 Address Transfer Start Signal
- 7.2.3 Address Transfer Signals
- 7.2.4 Address Transfer Attribute Signals
- 7.2.5 Address Transfer Termination Signals
- 7.2.6 Data Bus Arbitration Signals
- 7.2.7 Data Transfer Signals
- 7.2.8 Data Transfer Termination Signals
- Chapter 8 The 60x Bus
- 8.1 Terminology
- 8.2 Bus Configuration
- 8.3 60x Bus Protocol Overview
- 8.4 Address Tenure Operations
- 8.4.1 Address Arbitration
- 8.4.2 Address Pipelining
- 8.4.3 Address Transfer Attribute Signals
- 8.4.3.1 Transfer Type Signal (TT[0-4]) Encoding
- 8.4.3.2 Transfer Code Signals TC[0-2]
- 8.4.3.3 TBST and TSIZ[0-3] Signals and Size of Transfer
- 8.4.3.4 Burst Ordering During Data Transfers
- 8.4.3.5 Effect of Alignment on Data Transfers
- 8.4.3.6 Effect of Port Size on Data Transfers
- 8.4.3.7 60x-Compatible Bus Mode-Size Calculation
- 8.4.3.8 Extended Transfer Mode
- 8.4.4 Address Transfer Termination
- 8.4.5 Pipeline Control
- 8.5 Data Tenure Operations
- 8.6 Memory Coherency-MEI Protocol
- 8.7 Processor State Signals
- 8.8 Little-Endian Mode
- Chapter 9 PCI Bridge
- Figure 9-1. PCI Bridge in the PowerQUICC II
- Figure 9-2. PCI Bridge Structure
- 9.1 Signals
- 9.2 Clocking
- 9.3 PCI Bridge Initialization
- 9.4 SDMA Interface
- 9.5 Interrupts from PCI Bridge
- 9.6 60x Bus Arbitration Priority
- 9.7 60x Bus Masters
- 9.8 CompactPCI Hot Swap Specification Support
- 9.9 PCI Interface
- Table 9-1. PCI Terminology
- 9.9.1 PCI Interface Operation
- 9.9.1.1 Bus Commands
- 9.9.1.2 PCI Protocol Fundamentals
- 9.9.1.3 Bus Transactions
- 9.9.1.4 Other Bus Operations
- 9.9.1.5 Error Functions
- 9.9.2 PCI Bus Arbitration
- 9.10 Address Map
- Figure 9-11. Address Decode Flow Chart for 60x Bus Mastered Transactions
- Figure 9-12. Address Decode Flow Chart for PCI Mastered Transactions
- Figure 9-13. Address Decode Flow Chart for Embedded Utilities (DMA, Message Unit) Mastered Transactions
- Figure 9-14. Address Map Example
- 9.10.1 Address Map Programming
- 9.10.2 Address Translation
- 9.10.3 SIU Registers
- 9.11 Configuration Registers
- 9.11.1 Memory-Mapped Configuration Registers
- Table 9-3. Internal Memory Map (continued)
- 9.11.1.1 Message Unit (I2O) Registers
- 9.11.1.2 DMA Controller Registers
- 9.11.1.3 PCI Outbound Translation Address Registers (POTARx)
- 9.11.1.4 PCI Outbound Base Address Registers (POBARx)
- 9.11.1.5 PCI Outbound Comparison Mask Registers (POCMRx)
- 9.11.1.6 Discard Timer Control Register (PTCR)
- 9.11.1.7 General Purpose Control Register (GPCR)
- 9.11.1.8 PCI General Control Register (PCI_GCR)
- 9.11.1.9 Error Status Register (ESR)
- 9.11.1.10 Error Mask Register (EMR)
- 9.11.1.11 Error Control Register (ECR)
- 9.11.1.12 PCI Error Address Capture Register (PCI_EACR)
- 9.11.1.13 PCI Error Data Capture Register (PCI_EDCR)
- 9.11.1.14 PCI Error Control Capture Register (PCI_ECCR)
- 9.11.1.15 PCI Inbound Translation Address Registers (PITARx)
- 9.11.1.16 PCI Inbound Base Address Registers (PIBARx)
- 9.11.1.17 PCI Inbound Comparison Mask Registers (PICMRx)
- 9.11.2 PCI Bridge Configuration Registers
- Table 9-19. PCI Bridge PCI Configuration Registers (continued)
- Figure 9-32. PCI Bridge PCI Configuration Registers
- 9.11.2.1 Vendor ID Register
- 9.11.2.2 Device ID Register
- 9.11.2.3 PCI Bus Command Register
- 9.11.2.4 PCI Bus Status Register
- 9.11.2.5 Revision ID Register
- 9.11.2.6 PCI Bus Programming Interface Register
- 9.11.2.7 Subclass Code Register
- 9.11.2.8 PCI Bus Base Class Code Register
- 9.11.2.9 PCI Bus Cache Line Size Register
- 9.11.2.10 PCI Bus Latency Timer Register
- 9.11.2.11 Header Type Register
- 9.11.2.12 BIST Control Register
- 9.11.2.13 PCI Bus Internal Memory-Mapped Registers Base Address Register (PIMMRBAR)
- 9.11.2.14 General Purpose Local Access Base Address Registers (GPLABARx)
- 9.11.2.15 Subsystem Vendor ID Register
- 9.11.2.16 Subsystem Device ID Register
- 9.11.2.17 PCI Bus Capabilities Pointer Register
- 9.11.2.18 PCI Bus Interrupt Line Register
- 9.11.2.19 PCI Bus Interrupt Pin Register
- 9.11.2.20 PCI Bus MIN GNT
- 9.11.2.21 PCI Bus MAX LAT
- 9.11.2.22 PCI Bus Function Register
- 9.11.2.23 PCI Bus Arbiter Configuration Register
- 9.11.2.24 PCI Hot Swap Register Block
- 9.11.2.25 PCI Hot Swap Control Status Register
- 9.11.2.26 PCI Configuration Register Access from the Core
- 9.11.2.27 PCI Configuration Register Access in Big-Endian Mode
- 9.11.2.28 Initializing the PCI Configuration Registers
- 9.11.1 Memory-Mapped Configuration Registers
- 9.12 Message Unit (I2O)
- 9.12.1 Message Registers
- 9.12.2 Door Bell Registers
- 9.12.3 I2O Unit
- Figure 9-64. I2O Message Queue
- 9.12.3.1 PCI Configuration Identification
- 9.12.3.2 Inbound FIFOs
- 9.12.3.3 Outbound FIFOs
- 9.12.3.4 I2O Registers
- 9.12.3.4.1 Inbound FIFO Queue Port Register (IFQPR)
- 9.12.3.4.2 Outbound FIFO Queue Port Register (OFQPR)
- 9.12.3.4.3 Outbound Message Interrupt Status Register (OMISR)
- 9.12.3.4.4 Outbound Message Interrupt Mask Register (OMIMR)
- 9.12.3.4.5 Inbound Message Interrupt Status Register (IMISR)
- 9.12.3.4.6 Inbound Message Interrupt Mask Register (IMIMR)
- 9.12.3.4.7 Messaging Unit Control Register (MUCR)
- 9.12.3.4.8 Queue Base Address Register (QBAR)
- 9.13 DMA Controller
- Figure 9-81. DMA Controller Block Diagram
- 9.13.1 DMA Operation
- 9.13.1.1 DMA Direct Mode
- 9.13.1.2 DMA Chaining Mode
- 9.13.1.3 DMA Coherency
- 9.13.1.4 Halt and Error Conditions
- 9.13.1.5 DMA Transfer Types
- 9.13.1.6 DMA Registers
- 9.13.1.6.1 DMA Mode Register [0-3] (DMAMRx)
- 9.13.1.6.2 DMA Status Register [0-3] (DMASRx)
- 9.13.1.6.3 DMA Current Descriptor Address Register [0-3] (DMACDARx)
- 9.13.1.6.4 DMA Source Address Register [0-3] (DMASARx)
- 9.13.1.6.5 DMA Destination Address Register [0-3] (DMADARx)
- 9.13.1.6.6 DMA Byte Count Register [0-3] (DMABCRx)
- 9.13.1.6.7 DMA Next Descriptor Address Register [0-3] (DMANDARx)
- 9.13.2 DMA Segment Descriptors
- 9.14 Error Handling
- Chapter 10 Clocks and Power Control
- 10.1 Clock Unit
- 10.2 Clock Configuration
- 10.3 External Clock Inputs
- 10.4 Main PLL
- 10.5 Clock Dividers
- 10.6 PowerQUICC II Internal Clock Signals
- 10.7 PLL Pins
- 10.8 System Clock Control Register (SCCR)
- 10.9 System Clock Mode Register (SCMR)
- 10.10 Basic Power Structure
- Chapter 11 Memory Controller
- Figure 11-1. Dual-Bus Architecture
- 11.1 Features
- 11.2 Basic Architecture
- Figure 11-2. Memory Controller Machine Selection
- Figure 11-3. Simple System Configuration
- Figure 11-4. Basic Memory Controller Operation
- 11.2.1 Address and Address Space Checking
- 11.2.2 Page Hit Checking
- 11.2.3 Error Checking and Correction (ECC)
- 11.2.4 Parity Generation and Checking
- 11.2.5 Transfer Error Acknowledge (TEA) Generation
- 11.2.6 Machine Check Interrupt (MCP) Generation
- 11.2.7 Data Buffer Controls (BCTLx and LWR)
- 11.2.8 Atomic Bus Operation
- 11.2.9 Data Pipelining
- 11.2.10 External Memory Controller Support
- 11.2.11 External Address Latch Enable Signal (ALE)
- 11.2.12 ECC/Parity Byte Select (PBSE)
- 11.2.13 Partial Data Valid Indication (PSDVAL)
- 11.2.14 BADDR[27:31] Signal Connections
- 11.3 Register Descriptions
- Table 11-3. 60x Bus Memory Controller Registers
- 11.3.1 Base Registers (BRx)
- 11.3.2 Option Registers (ORx)
- 11.3.3 60x SDRAM Mode Register (PSDMR)
- 11.3.4 Local Bus SDRAM Mode Register (LSDMR)
- 11.3.5 Machine A/B/C Mode Registers (MxMR)
- 11.3.6 Memory Data Register (MDR)
- 11.3.7 Memory Address Register (MAR)
- 11.3.8 60x Bus-Assigned UPM Refresh Timer (PURT)
- 11.3.9 Local Bus-Assigned UPM Refresh Timer (LURT)
- 11.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
- 11.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT)
- 11.3.12 Memory Refresh Timer Prescaler Register (MPTPR)
- 11.3.13 60x Bus Error Status and Control Registers (TESCRx)
- 11.3.14 Local Bus Error Status and Control Registers (L_TESCRx)
- 11.4 SDRAM Machine
- Table 11-18. SDRAM Interface Signals
- Figure 11-19. 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown)
- 11.4.1 Supported SDRAM Configurations
- 11.4.2 SDRAM Power-On Initialization
- 11.4.3 JEDEC-Standard SDRAM Interface Commands
- 11.4.4 Page-Mode Support and Pipeline Accesses
- 11.4.5 Bank Interleaving
- 11.4.6 SDRAM Device-Specific Parameters
- 11.4.6.1 Precharge-to-Activate Interval
- 11.4.6.2 Activate to Read/Write Interval
- 11.4.6.3 Column Address to First Data Out-CAS Latency
- 11.4.6.4 Last Data Out to Precharge
- 11.4.6.5 Last Data In to Precharge-Write Recovery
- 11.4.6.6 Refresh Recovery Interval (RFRC)
- 11.4.6.7 External Address Multiplexing Signal
- 11.4.6.8 External Address and Command Buffers (BUFCMD)
- 11.4.7 SDRAM Interface Timing
- Figure 11-28. SDRAM Single-Beat Read, Page Closed, CL = 3
- Figure 11-29. SDRAM Single-Beat Read, Page Hit, CL = 3
- Figure 11-30. SDRAM Two-Beat Burst Read, Page Closed, CL = 3
- Figure 11-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3
- Figure 11-32. SDRAM Single-Beat Write, Page Hit
- Figure 11-33. SDRAM Three-Beat Burst Write, Page Closed
- Figure 11-34. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3
- Figure 11-35. SDRAM Write-after-Write Pipelined, Page Hit
- Figure 11-36. SDRAM Read-after-Write Pipelined, Page Hit
- 11.4.8 SDRAM Read/Write Transactions
- 11.4.9 SDRAM Mode-Set Command Timing
- 11.4.10 SDRAM Refresh
- 11.4.11 SDRAM Refresh Timing
- 11.4.12 SDRAM Configuration Examples
- 11.4.13 SDRAM Configuration Example (Bank-Based Interleaving)
- 11.5 General-Purpose Chip-Select Machine (GPCM)
- Table 11-30. GPCM Interfaces Signals
- Figure 11-40. GPCM-to-SRAM Configuration
- 11.5.1 Timing Configuration
- Table 11-31. GPCM Strobe Signal Behavior
- 11.5.1.1 Chip-Select Assertion Timing
- 11.5.1.2 Chip-Select and Write Enable Deassertion Timing
- 11.5.1.3 Relaxed Timing
- Figure 11-46. GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1)
- Figure 11-47. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,TRLX = 1)
- Figure 11-48. GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1)
- Figure 11-49. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1)
- 11.5.1.4 Output Enable (OE) Timing
- 11.5.1.5 Programmable Wait State Configuration
- 11.5.1.6 Extended Hold Time on Read Accesses
- 11.5.2 External Access Termination
- 11.5.3 Boot Chip-Select Operation
- 11.5.4 Differences between MPC8xx’s GPCM and MPC82xx’s GPCM
- 11.6 User-Programmable Machines (UPMs)
- Table 11-34. UPM Interfaces Signals
- Figure 11-55. User-Programmable Machine Block Diagram
- 11.6.1 Requests
- 11.6.2 Programming the UPMs
- 11.6.3 Clock Timing
- 11.6.4 The RAM Array
- Figure 11-61. RAM Array and Signal Generation
- 11.6.4.1 RAM Words
- 11.6.4.2 Address Multiplexing
- 11.6.4.3 Data Valid and Data Sample Control
- 11.6.4.4 Signals Negation
- 11.6.4.5 The Wait Mechanism
- 11.6.4.6 Extended Hold Time on Read Accesses
- 11.6.5 UPM DRAM Configuration Example
- 11.6.6 Differences between MPC8xx UPM and MPC82xx UPM
- 11.7 Memory System Interface Example Using UPM
- Figure 11-67. DRAM Interface Connection to the 60x Bus (64-Bit Port Size)
- Table 11-42. UPMs Attributes Example
- Figure 11-68. Single-Beat Read Access to FPM DRAM
- Figure 11-69. Single-Beat Write Access to FPM DRAM
- Figure 11-70. Burst Read Access to FPM DRAM (No LOOP)
- Figure 11-71. Burst Read Access to FPM DRAM (LOOP)
- Figure 11-72. Burst Write Access to FPM DRAM (No LOOP)
- Figure 11-73. Refresh Cycle (CBR) to FPM DRAM
- Figure 11-74. Exception Cycle
- Table 11-43. UPMs Attributes Example
- Figure 11-75. FPM DRAM Burst Read Access (Data Sampling on Falling Edge of CLKIN)
- 11.7.0.1 EDO Interface Example
- Figure 11-76. PowerQUICC II/EDO Interface Connection to the 60x Bus
- Table 11-44. EDO Connection Field Value Example (continued)
- Figure 11-77. Single-Beat Read Access to EDO DRAM
- Figure 11-78. Single-Beat Write Access to EDO DRAM
- Figure 11-79. Single-Beat Write Access to EDO DRAM Using REDO to Insert Three Wait States
- Figure 11-80. Burst Read Access to EDO DRAM
- Figure 11-81. Burst Write Access to EDO DRAM
- Figure 11-82. Refresh Cycle (CBR) to EDO DRAM
- Figure 11-83. Exception Cycle For EDO DRAM
- 11.8 Handling Devices with Slow or Variable Access Times
- 11.9 External Master Support (60x-Compatible Mode)
- Chapter 12 Secondary (L2) Cache Support
- Chapter 13 IEEE 1149.1 Test Access Port
- Part IV Communications Processor Module
- Chapter 14 Communications Processor Module Overview
- 14.1 Features
- 14.2 PowerQUICC II Serial Configurations
- 14.3 Communications Processor (CP)
- 14.3.1 CPM Performance Evaluation
- 14.3.2 Features
- 14.3.3 CP Block Diagram
- 14.3.4 G2 Core Interface
- 14.3.5 Peripheral Interface
- 14.3.6 Execution from RAM
- 14.3.7 RISC Controller Configuration Register (RCCR)
- 14.3.8 RISC Time-Stamp Control Register (RTSCR)
- 14.3.9 RISC Time-Stamp Register (RTSR)
- 14.3.10 RISC Microcode Revision Number
- 14.4 Command Set
- 14.5 Dual-Port RAM
- 14.6 RISC Timer Tables
- 14.6.1 RISC Timer Table Parameter RAM
- 14.6.2 RISC Timer Command Register (TM_CMD)
- 14.6.3 RISC Timer Table Entries
- 14.6.4 RISC Timer Event Register (RTER)/Mask Register (RTMR)
- 14.6.5 set timer Command
- 14.6.6 RISC Timer Initialization Sequence
- 14.6.7 RISC Timer Initialization Example
- 14.6.8 RISC Timer Interrupt Handling
- 14.6.9 RISC Timer Table Scan Algorithm
- 14.6.10 Using the RISC Timers to Track CP Loading
- Chapter 15 Serial Interface with Time-Slot Assigner
- Figure 15-1. SI Block Diagram
- 15.1 Features
- 15.2 Overview
- 15.3 Enabling Connections to TSA
- 15.4 Serial Interface RAM
- 15.5 Serial Interface Registers
- 15.5.1 SI Global Mode Registers (SIxGMR)
- 15.5.2 SI Mode Registers (SIxMR)
- Figure 15-11. SI Mode Registers (SIxMR)
- Table 15-5. SIxMR Field Descriptions (continued)
- Figure 15-12. One-Clock Delay from Sync to Data (xFSD = 01)
- Figure 15-13. No Delay from Sync to Data (xFSD = 00)
- Figure 15-14. Falling Edge (FE) Effect When CE = 1 and xFSD = 01
- Figure 15-15. Falling Edge (FE) Effect When CE = 0 and xFSD = 01
- Figure 15-16. Falling Edge (FE) Effect When CE = 1 and xFSD = 00
- Figure 15-17. Falling Edge (FE) Effect When CE = 0 and xFSD = 00
- 15.5.3 SIx RAM Shadow Address Registers (SIxRSR)
- 15.5.4 SI Command Register (SIxCMDR)
- 15.5.5 SI Status Registers (SIxSTR)
- 15.6 Serial Interface IDL Interface Support
- 15.7 Serial Interface GCI Support
- Chapter 16 CPM Multiplexing
- Figure 16-1. CPM Multiplexing Logic (CMX) Block Diagram
- 16.1 Features
- 16.2 Enabling Connections to TSA or NMSI
- 16.3 NMSI Configuration
- 16.4 CMX Registers
- Chapter 17 Baud-Rate Generators (BRGs)
- Chapter 18 Timers
- Figure 18-1. Timer Block Diagram
- 18.1 Features
- 18.2 General-Purpose Timer Units
- Chapter 19 SDMA Channels and IDMA Emulation
- Figure 19-1. SDMA Data Paths
- 19.1 SDMA Bus Arbitration and Bus Transfers
- 19.2 SDMA Registers
- 19.3 IDMA Emulation
- 19.4 IDMA Features
- 19.5 IDMA Transfers
- 19.6 IDMA Priorities
- 19.7 IDMA Interface Signals
- 19.8 IDMA Operation
- 19.8.1 Auto Buffer and Buffer Chaining
- 19.8.2 IDMAx Parameter RAM
- 19.8.3 IDMA Performance
- 19.8.4 IDMA Event Register (IDSR) and Mask Register (IDMR)
- 19.8.5 IDMA BDs
- 19.9 IDMA Commands
- 19.10 IDMA Bus Exceptions
- 19.11 Programming the Parallel I/O Registers
- 19.12 IDMA Programming Examples
- Chapter 20 Serial Communications Controllers (SCCs)
- Figure 20-1. SCC Block Diagram
- 20.1 Features
- 20.2 SCC Buffer Descriptors (BDs)
- 20.3 SCC Parameter RAM
- Table 20-4. SCC Parameter RAM Map for All Protocols (continued)
- 20.3.1 SCC Base Addresses
- 20.3.2 Function Code Registers (RFCR and TFCR)
- 20.3.3 Handling SCC Interrupts
- 20.3.4 Initializing the SCCs
- 20.3.5 Controlling SCC Timing with RTS, CTS, and CD
- 20.3.6 Digital Phase-Locked Loop (DPLL) Operation
- 20.3.7 Reconfiguring the SCCs
- 20.3.8 Saving Power
- Chapter 21 SCC UART Mode
- Figure 21-1. UART Character Format
- 21.1 Features
- 21.2 Normal Asynchronous Mode
- 21.3 Synchronous Mode
- 21.4 SCC UART Parameter RAM
- 21.5 Data-Handling Methods: Character- or Message-Based
- 21.6 Error and Status Reporting
- 21.7 SCC UART Commands
- 21.8 Multidrop Systems and Address Recognition
- 21.9 Receiving Control Characters
- 21.10 Hunt Mode (Receiver)
- 21.11 Inserting Control Characters into the Transmit Data Stream
- 21.12 Sending a Break (Transmitter)
- 21.13 Sending a Preamble (Transmitter)
- 21.14 Fractional Stop Bits (Transmitter)
- 21.15 Handling Errors in the SCC UART Controller
- 21.16 UART Mode Register (PSMR)
- 21.17 SCC UART Receive Buffer Descriptor (RxBD)
- 21.18 SCC UART Transmit Buffer Descriptor (TxBD)
- 21.19 SCC UART Event Register (SCCE) and Mask Register (SCCM)
- 21.20 SCC UART Status Register (SCCS)
- 21.21 SCC UART Programming Example
- 21.22 S-Records Loader Application
- Chapter 22 SCC HDLC Mode
- 22.1 SCC HDLC Features
- 22.2 SCC HDLC Channel Frame Transmission
- 22.3 SCC HDLC Channel Frame Reception
- 22.4 SCC HDLC Parameter RAM
- 22.5 Programming the SCC in HDLC Mode
- 22.6 SCC HDLC Commands
- 22.7 Handling Errors in the SCC HDLC Controller
- 22.8 HDLC Mode Register (PSMR)
- 22.9 SCC HDLC Receive Buffer Descriptor (RxBD)
- 22.10 SCC HDLC Transmit Buffer Descriptor (TxBD)
- 22.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)
- 22.12 SCC HDLC Status Register (SCCS)
- 22.13 SCC HDLC Programming Examples
- 22.14 SCC HDLC Programming Example #1
- 22.15 HDLC Bus Mode with Collision Detection
- Figure 22-10. Typical HDLC Bus Multimaster Configuration
- Figure 22-11. Typical HDLC Bus Single-Master Configuration
- 22.15.1 HDLC Bus Features
- 22.15.2 Accessing the HDLC Bus
- 22.15.3 Increasing Performance
- 22.15.4 Delayed RTS Mode
- 22.15.5 Using the Time-Slot Assigner (TSA)
- 22.15.6 HDLC Bus Protocol Programming
- Chapter 23 SCC BISYNC Mode
- Figure 23-1. Classes of BISYNC Frames
- 23.1 Features
- 23.2 SCC BISYNC Channel Frame Transmission
- 23.3 SCC BISYNC Channel Frame Reception
- 23.4 SCC BISYNC Parameter RAM
- 23.5 SCC BISYNC Commands
- 23.6 SCC BISYNC Control Character Recognition
- 23.7 BISYNC SYNC Register (BSYNC)
- 23.8 SCC BISYNC DLE Register (BDLE)
- 23.9 Sending and Receiving the Synchronization Sequence
- 23.10 Handling Errors in the SCC BISYNC
- 23.11 BISYNC Mode Register (PSMR)
- 23.12 SCC BISYNC Receive BD (RxBD)
- 23.13 SCC BISYNC Transmit BD (TxBD)
- 23.14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)
- 23.15 SCC Status Registers (SCCS)
- 23.16 Programming the SCC BISYNC Controller
- 23.17 SCC BISYNC Programming Example
- Chapter 24 SCC Transparent Mode
- 24.1 Features
- 24.2 SCC Transparent Channel Frame Transmission Process
- 24.3 SCC Transparent Channel Frame Reception Process
- 24.4 Achieving Synchronization in Transparent Mode
- 24.5 CRC Calculation in Transparent Mode
- 24.6 SCC Transparent Parameter RAM
- 24.7 SCC Transparent Commands
- 24.8 Handling Errors in the Transparent Controller
- 24.9 Transparent Mode and the PSMR
- 24.10 SCC Transparent Receive Buffer Descriptor (RxBD)
- 24.11 SCC Transparent Transmit Buffer Descriptor (TxBD)
- 24.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)
- 24.13 SCC Status Register in Transparent Mode (SCCS)
- 24.14 SCC2 Transparent Programming Example
- Chapter 25 SCC Ethernet Mode
- Figure 25-1. Ethernet Frame Structure
- 25.1 Ethernet on the PowerQUICC II
- 25.2 Features
- 25.3 Connecting the PowerQUICC II to Ethernet
- 25.4 SCC Ethernet Channel Frame Transmission
- 25.5 SCC Ethernet Channel Frame Reception
- 25.6 The Content-Addressable Memory (CAM) Interface
- 25.7 SCC Ethernet Parameter RAM
- 25.8 Programming the Ethernet Controller
- 25.9 SCC Ethernet Commands
- 25.10 SCC Ethernet Address Recognition
- 25.11 Hash Table Algorithm
- 25.12 Interpacket Gap Time
- 25.13 Handling Collisions
- 25.14 Internal and External Loopback
- 25.15 Full-Duplex Ethernet Support
- 25.16 Handling Errors in the Ethernet Controller
- 25.17 Ethernet Mode Register (PSMR)
- 25.18 SCC Ethernet Receive BD
- 25.19 SCC Ethernet Transmit Buffer Descriptor
- 25.20 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)
- 25.21 SCC Ethernet Programming Example
- Chapter 26 SCC AppleTalk Mode
- Chapter 27 Serial Management Controllers (SMCs)
- Figure 27-1. SMC Block Diagram
- 27.1 Features
- 27.2 Common SMC Settings and Configurations
- 27.3 SMC in UART Mode
- Figure 27-5. SMC UART Frame Format
- 27.3.1 Features
- 27.3.2 SMC UART Channel Transmission Process
- 27.3.3 SMC UART Channel Reception Process
- 27.3.4 Programming the SMC UART Controller
- 27.3.5 SMC UART Transmit and Receive Commands
- 27.3.6 Sending a Break
- 27.3.7 Sending a Preamble
- 27.3.8 Handling Errors in the SMC UART Controller
- 27.3.9 SMC UART RxBD
- 27.3.10 SMC UART TxBD
- 27.3.11 SMC UART Event Register (SMCE)/Mask Register (SMCM)
- 27.3.12 SMC UART Controller Programming Example
- 27.4 SMC in Transparent Mode
- 27.4.1 Features
- 27.4.2 SMC Transparent Channel Transmission Process
- 27.4.3 SMC Transparent Channel Reception Process
- 27.4.4 Using SMSYN for Synchronization
- 27.4.5 Using the Time-Slot Assigner (TSA) for Synchronization
- 27.4.6 SMC Transparent Commands
- 27.4.7 Handling Errors in the SMC Transparent Controller
- 27.4.8 SMC Transparent RxBD
- 27.4.9 SMC Transparent TxBD
- 27.4.10 SMC Transparent Event Register (SMCE)/Mask Register (SMCM)
- 27.4.11 SMC Transparent NMSI Programming Example
- 27.5 The SMC in GCI Mode
- 27.5.1 SMC GCI Parameter RAM
- 27.5.2 Handling the GCI Monitor Channel
- 27.5.3 Handling the GCI C/I Channel
- 27.5.4 SMC GCI Commands
- 27.5.5 SMC GCI Monitor Channel RxBD
- 27.5.6 SMC GCI Monitor Channel TxBD
- 27.5.7 SMC GCI C/I Channel RxBD
- 27.5.8 SMC GCI C/I Channel TxBD
- 27.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM)
- Chapter 28 Multi-Channel Controllers (MCCs)
- 28.1 MCC Operation Overview
- 28.2 Global MCC Parameters
- 28.3 Channel-Specific Parameters
- 28.3.1 Channel-Specific HDLC Parameters
- 28.3.2 Channel-Specific Transparent Parameters
- Table 28-6. Channel-Specific Parameters for Transparent Operation (continued)
- 28.3.2.1 Internal Transmitter State (TSTATE)-Transparent Mode
- 28.3.2.2 Interrupt Mask (INTMSK)-Transparent Mode
- 28.3.2.3 Channel Mode Register (CHAMR)-Transparent Mode
- 28.3.2.4 Internal Receiver State (RSTATE)-Transparent Mode
- 28.3.3 MCC Parameters for AAL1 CES Usage
- 28.3.4 Channel-Specific SS7 Parameters
- 28.4 Channel Extra Parameters
- 28.5 Superchannels
- 28.6 MCC Configuration Registers (MCCFx)
- 28.7 MCC Commands
- 28.8 MCC Exceptions
- Figure 28-18. Interrupt Circular Table
- 28.8.1 MCC Event Register (MCCE)/Mask Register (MCCM)
- 28.9 MCC Buffer Descriptors
- 28.10 MCC Initialization and Start/Stop Sequence
- 28.11 MCC Latency and Performance
- Chapter 29 Fast Communications Controllers (FCCs)
- 29.1 Overview
- 29.2 General FCC Mode Registers (GFMRx)
- 29.3 FCC Protocol-Specific Mode Registers (FPSMRx)
- 29.4 FCC Data Synchronization Registers (FDSRx)
- 29.5 FCC Transmit-on-Demand Registers (FTODRx)
- 29.6 FCC Buffer Descriptors
- 29.7 FCC Parameter RAM
- 29.8 Interrupts from the FCCs
- 29.9 FCC Initialization
- 29.10 FCC Interrupt Handling
- 29.11 FCC Timing Control
- 29.12 Disabling the FCCs On-the-Fly
- 29.13 Saving Power
- Chapter 30 ATM Controller and AAL0, AAL1, and AAL5
- 30.1 Features
- 30.2 ATM Controller Overview
- 30.3 ATM Pace Control (APC) Unit
- 30.3.1 APC Modes and ATM Service Types
- 30.3.2 APC Unit Scheduling Mechanism
- 30.3.3 Determining the Scheduling Table Size
- 30.3.4 Determining the Time-Slot Scheduling Rate of a Channel
- 30.3.5 ATM Traffic Type
- 30.3.6 Determining the Priority of an ATM Channel
- 30.4 VCI/VPI Address Lookup Mechanism
- 30.4.1 External CAM Lookup
- 30.4.2 Address Compression
- 30.4.3 Misinserted Cells
- 30.4.4 Receive Raw Cell Queue
- 30.5 Available Bit Rate (ABR) Flow Control
- 30.6 OAM Support
- 30.7 User-Defined Cells (UDC)
- 30.8 ATM Layer Statistics
- 30.9 ATM-to-TDM Interworking
- 30.10 ATM Memory Structure
- 30.10.1 Parameter RAM
- 30.10.2 Connection Tables (RCT, TCT, and TCTE)
- Table 30-15. Receive and Transmit Connection Table Sizes
- 30.10.2.1 ATM Channel Code
- 30.10.2.2 Receive Connection Table (RCT)
- Figure 30-25. Receive Connection Table (RCT) Entry
- Table 30-16. RCT Field Descriptions (continued)
- 30.10.2.2.1 AAL5 Protocol-Specific RCT
- 30.10.2.2.2 AAL5-ABR Protocol-Specific RCT
- 30.10.2.2.3 AAL1 Protocol-Specific RCT
- 30.10.2.2.4 AAL0 Protocol-Specific RCT
- 30.10.2.2.5 AAL1 CES Protocol-Specific RCT
- 30.10.2.2.6 AAL2 Protocol-Specific RCT
- 30.10.2.3 Transmit Connection Table (TCT)
- Figure 30-30. Transmit Connection Table (TCT) Entry
- Table 30-21. TCT Field Descriptions (continued)
- 30.10.2.3.1 AAL5 Protocol-Specific TCT
- 30.10.2.3.2 AAL1 Protocol-Specific TCT
- 30.10.2.3.3 AAL0 Protocol-Specific TCT
- 30.10.2.3.4 AAL1 CES Protocol-Specific TCT
- 30.10.2.3.5 AAL2 Protocol-Specific TCT
- 30.10.2.3.6 VBR Protocol-Specific TCTE
- 30.10.2.3.7 UBR+ Protocol-Specific TCTE
- 30.10.2.3.8 ABR Protocol-Specific TCTE
- 30.10.3 OAM Performance Monitoring Tables
- 30.10.4 APC Data Structure
- 30.10.5 ATM Controller Buffer Descriptors (BDs)
- 30.10.5.1 Transmit Buffer Operation
- 30.10.5.2 Receive Buffer Operation
- 30.10.5.3 ATM Controller Buffers
- 30.10.5.4 AAL5 RxBD
- 30.10.5.5 AAL1 RxBD
- 30.10.5.6 AAL0 RxBD
- 30.10.5.7 AAL1 CES RxBD
- 30.10.5.8 AAL2 RxBD
- 30.10.5.9 AAL5, AAL1 CES User-Defined Cell-RxBD Extension
- 30.10.5.10 AAL5 TxBDs
- 30.10.5.11 AAL1 TxBDs
- 30.10.5.12 AAL0 TxBDs
- 30.10.5.13 AAL1 CES TxBDs
- 30.10.5.14 AAL2 TxBDs
- 30.10.5.15 AAL5, AAL1 User-Defined Cell-TxBD Extension
- 30.10.6 AAL1 Sequence Number (SN) Protection Table
- 30.10.7 UNI Statistics Table
- 30.11 ATM Exceptions
- 30.12 The UTOPIA Interface
- 30.13 ATM Registers
- 30.14 ATM Transmit Command
- 30.15 SRTS Generation and Clock Recovery Using External Logic
- 30.16 Configuring the ATM Controller for Maximum CPM Performance
- Chapter 31 ATM AAL1 Circuit Emulation Service
- 31.1 Features
- 31.2 AAL1 CES Transmitter Overview
- 31.3 AAL1 CES Receiver Overview
- 31.4 Interworking Functions
- 31.4.1 Automatic Data Forwarding
- 31.4.2 Timing Issues
- 31.4.3 Clock Synchronization (SRTS, Adaptive FIFO)
- 31.4.4 Mapping TDM Time Slots to VCs
- 31.4.5 Trunk Condition
- 31.4.6 Channel Associated Signaling (CAS) Support
- 31.4.7 Mapping VC Signaling to CAS Blocks
- 31.5 ATM-to-TDM Adaptive Slip Control
- 31.6 3-Step-SN Algorithm
- 31.7 Pointer Verification Mechanism
- 31.8 AAL-1 Memory Structure
- 31.9 Receive and Transmit Connection Tables (RCT, TCT)
- 31.10 Outgoing CAS Status Register (OCASSR)
- 31.11 Buffer Descriptors
- 31.12 ATM Controller Buffers
- 31.13 AAL1 CES Exceptions
- 31.14 AAL1 Sequence Number (SN) Protection Table
- 31.15 Internal AAL1 CES Statistics Tables
- 31.16 External AAL1 CES Statistics Tables
- 31.17 CES-Specific Additions to the MCC
- 31.18 Application Considerations
- Chapter 32 ATM AAL2
- 32.1 Introduction
- 32.2 Features
- 32.3 AAL2 Transmitter
- 32.3.1 Transmitter Overview
- 32.3.2 Transmit Priority Mechanism
- 32.3.3 Partial Fill Mode (PFM)
- 32.3.4 No STF Mode
- 32.3.5 AAL2 Tx Data Structures
- 32.4 AAL2 Receiver
- 32.4.1 Receiver Overview
- 32.4.2 Mapping of PHY | VP | VC | CID
- 32.4.3 AAL2 Switching
- 32.4.4 AAL2 RX Data Structures
- 32.4.4.1 AAL2 Protocol-Specific RCT
- 32.4.4.2 CID Mapping Tables and RxQDs
- 32.4.4.3 CPS Rx Queue Descriptors
- 32.4.4.4 CPS Receive Buffer Descriptor (RxBD)
- 32.4.4.5 CPS Switch Rx Queue Descriptor
- 32.4.4.6 SWITCH Receive/Transmit Buffer Descriptor (RxBD)
- 32.4.4.7 SSSAR Rx Queue Descriptor
- 32.4.4.8 SSSAR Receive Buffer Descriptor
- 32.5 AAL2 Parameter RAM
- 32.6 User-Defined Cells in AAL2
- 32.7 AAL2 Exceptions
- Chapter 33 Inverse Multiplexing for ATM (IMA)
- 33.1 Features
- 33.2 IMA Protocol Overview
- 33.3 IMA Microcode Architecture
- 33.4 IMA Programming Model
- 33.4.1 Data Structure Organization
- 33.4.2 IMA FCC Programming
- 33.4.3 IMA Root Table
- 33.4.4 IMA Group Tables
- 33.4.4.1 IMA Group Transmit Table Entry
- 33.4.4.2 IMA Group Receive Table Entry
- 33.4.5 IMA Link Tables
- 33.4.5.1 IMA Link Transmit Table Entry
- 33.4.5.2 IMA Link Receive Table Entry
- 33.4.5.3 IMA Link Receive Statistics Table
- 33.4.6 Structures in External Memory
- 33.4.7 IMA Exceptions
- 33.4.8 IDCR Timer Programming
- 33.4.9 APC Programming for IMA
- 33.4.10 Changing IMA Version
- 33.5 IMA Software Interface and Requirements
- 33.5.1 Software Model
- 33.5.2 Initialization Procedure
- 33.5.3 Software Responsibilities
- 33.5.3.1 System Definition
- 33.5.3.2 General Operation
- 33.5.3.3 Receive Link State Machine Control
- 33.5.3.4 Receive Group State Machine Control
- 33.5.3.5 Transmit Link State Machine Control
- 33.5.3.6 Transmit Group State Machine Control
- 33.5.3.7 Group Symmetry Control
- 33.5.3.8 ICP End-to-End Channel Transmission
- 33.5.3.9 Link Addition and Slow Recovery (LASR) Procedure
- 33.5.3.10 Failure Alarms
- 33.5.3.11 Test Pattern Control
- 33.5.3.12 Performance Parameter Measurement and Reporting
- 33.5.3.13 SNMP MIBs
- 33.5.4 IMA Software Procedures
- 33.5.4.1 Transmit ICP Cell Signalling
- 33.5.4.2 Receive Link Start-up Procedure
- 33.5.4.3 Group Start-up Procedure
- 33.5.4.4 Link Addition Procedure
- 33.5.4.5 Link Removal Procedure
- 33.5.4.6 Link Receive Deactivation Procedure
- 33.5.4.7 Link Receive Reactivation Procedure
- 33.5.4.8 TRL On-the-Fly Change Procedure
- 33.5.4.9 Transmit Event Response Procedures
- 33.5.4.10 Receive Event Response Procedures
- 33.5.4.11 Test Pattern Procedure
- 33.5.4.12 IDCR Operation
- 33.5.4.13 End-to-End Channel Signalling Procedure
- Chapter 34 ATM Transmission Convergence Layer
- Figure 34-1. Serial ATM Using FCC2 and TC Blocks (Single Channel)
- 34.1 Features
- 34.2 Functionality
- 34.3 Signals
- 34.4 TC Layer Programming Mode
- 34.4.1 TC Layer Registers
- 34.4.2 TC Layer General Registers
- 34.4.3 TC Layer Cell Counters
- 34.4.4 Programming FCC2
- 34.4.5 Programming and Operating the TC Layer
- 34.5 Implementation Example
- Chapter 35 Fast Ethernet Controller
- Figure 35-1. Ethernet Frame Structure
- 35.1 Fast Ethernet on the PowerQUICC II
- 35.2 Features
- 35.3 Connecting the PowerQUICC II to Fast Ethernet
- 35.4 Ethernet Channel Frame Transmission
- 35.5 Ethernet Channel Frame Reception
- 35.6 Flow Control
- 35.7 CAM Interface
- 35.8 Ethernet Parameter RAM
- 35.9 Programming Model
- 35.10 Ethernet Command Set
- 35.11 RMON Support
- 35.12 Ethernet Address Recognition
- 35.13 Hash Table Algorithm
- 35.14 Interpacket Gap Time
- 35.15 Handling Collisions
- 35.16 Internal and External Loopback
- 35.17 Ethernet Error-Handling Procedure
- 35.18 Fast Ethernet Registers
- 35.19 Ethernet RxBDs
- 35.20 Ethernet TxBDs
- Chapter 36 FCC HDLC Controller
- 36.1 Key Features
- 36.2 HDLC Channel Frame Transmission Processing
- 36.3 HDLC Channel Frame Reception Processing
- 36.4 HDLC Parameter RAM
- 36.5 Programming Model
- 36.6 HDLC Mode Register (FPSMR)
- 36.7 HDLC Receive Buffer Descriptor (RxBD)
- 36.8 HDLC Transmit Buffer Descriptor (TxBD)
- 36.9 HDLC Event Register (FCCE)/Mask Register (FCCM)
- 36.10 FCC Status Register (FCCS)
- Chapter 37 FCC Transparent Controller
- Chapter 38 Serial Peripheral Interface (SPI)
- Figure 38-1. SPI Block Diagram
- 38.1 Features
- 38.2 SPI Clocking and Signal Functions
- 38.3 Configuring the SPI Controller
- 38.4 Programming the SPI Registers
- 38.5 SPI Parameter RAM
- 38.6 SPI Commands
- 38.7 The SPI Buffer Descriptor (BD) Table
- 38.8 SPI Master Programming Example
- 38.9 SPI Slave Programming Example
- 38.10 Handling Interrupts in the SPI
- Chapter 39 I2C Controller
- Figure 39-1. I2C Controller Block Diagram
- 39.1 Features
- 39.2 I2C Controller Clocking and Signal Functions
- 39.3 I2C Controller Transfers
- 39.4 I2C Registers
- 39.5 I2C Parameter RAM
- 39.6 I2C Commands
- 39.7 The I2C Buffer Descriptor (BD) Table
- Chapter 40 Parallel I/O Ports
- 40.1 Features
- 40.2 Port Registers
- 40.3 Port Block Diagram
- 40.4 Port Pins Functions
- 40.5 Ports Tables
- Figure 40-7. Primary and Secondary Option Programming
- Table 40-5. Port A-Dedicated Pin Assignment (PPARA = 1) (continued)
- Table 40-6. Port B Dedicated Pin Assignment (PPARB = 1) (continued)
- Table 40-7. Port C Dedicated Pin Assignment (PPARC = 1) (continued)
- Table 40-8. Port D Dedicated Pin Assignment (PPARD = 1) (continued)
- 40.6 Interrupts from Port C
- Appendix A Register Quick Reference Guide
- Appendix B Reference Manual (Rev 1) Errata
- Glossary
- Index