Freescale Semiconductor MPC8260 - Manual (Page 41)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor xxxix
Contents
Paragraph
Number
Title
Page
Number
33.5.4.3.2 As Responder (RX) ......................................................................................... 33-65
33.5.4.4 Link Addition Procedure ..................................................................................... 33-65
33.5.4.4.1 Rx Steps ........................................................................................................... 33-65
33.5.4.4.2 TX Parameters ................................................................................................. 33-66
33.5.4.5 Link Removal Procedure ..................................................................................... 33-67
33.5.4.5.1 Rx Steps ........................................................................................................... 33-67
33.5.4.5.2 TX Parameters ................................................................................................. 33-68
33.5.4.6 Link Receive Deactivation Procedure ................................................................. 33-68
33.5.4.7 Link Receive Reactivation Procedure ................................................................. 33-69
33.5.4.8 TRL On-the-Fly Change Procedure..................................................................... 33-69
33.5.4.9 Transmit Event Response Procedures.................................................................. 33-70
33.5.4.10 Receive Event Response Procedures ................................................................... 33-70
33.5.4.11 Test Pattern Procedure ......................................................................................... 33-72
33.5.4.11.1 As Initiator (NE).............................................................................................. 33-72
33.5.4.11.2 As Responder (FE) .......................................................................................... 33-72
33.5.4.12 IDCR Operation................................................................................................... 33-73
33.5.4.12.1 IDCR Start-up.................................................................................................. 33-73
33.5.4.12.2 Activating a Group in IDCR Mode ................................................................. 33-74
33.5.4.13 End-to-End Channel Signalling Procedure.......................................................... 33-74
33.5.4.13.1 Transmit ........................................................................................................... 33-74
33.5.4.13.2 Receive ............................................................................................................ 33-75
Chapter 34
ATM Transmission Convergence Layer
34.1 Features .......................................................................................................................... 34-1
34.2 Functionality .................................................................................................................. 34-3
34.2.1 Receive ATM Cell Functions..................................................................................... 34-4
34.2.1.1 Receive ATM 2-Cell FIFO .................................................................................... 34-6
34.2.2 Transmit ATM Cell Functions ................................................................................... 34-6
34.2.2.1 Transmit ATM 2-Cell FIFO ................................................................................... 34-6
34.2.3 Receive UTOPIA Interface........................................................................................ 34-7
34.2.4 Transmit UTOPIA Interface ...................................................................................... 34-7
34.3 Signals............................................................................................................................ 34-7
34.4 TC Layer Programming Mode ...................................................................................... 34-7
34.4.1 TC Layer Registers .................................................................................................... 34-7
34.4.1.1 TC Layer Mode Register [1–8] (TCMODEx) ....................................................... 34-7
34.4.1.2 Cell Delineation State Machine Register [1–8] (CDSMRx).................................. 34-9
34.4.1.3 TC Layer Event Register [1–8] (TCERx)............................................................ 34-10
34.4.1.4 TC Layer Mask Register (TCMRx)..................................................................... 34-11
34.4.2 TC Layer General Registers .................................................................................... 34-11