Freescale Semiconductor MPC8260 - Manual (Page 22)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
xx Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
14.6.7 RISC Timer Initialization Example ......................................................................... 14-26
14.6.8 RISC Timer Interrupt Handling ............................................................................... 14-26
14.6.9 RISC Timer Table Scan Algorithm.......................................................................... 14-26
14.6.10 Using the RISC Timers to Track CP Loading ......................................................... 14-27
Chapter 15
Serial Interface with Time-Slot Assigner
15.1 Features .......................................................................................................................... 15-3
15.2 Overview........................................................................................................................ 15-4
15.3 Enabling Connections to TSA ....................................................................................... 15-7
15.4 Serial Interface RAM ..................................................................................................... 15-8
15.4.1 One Multiplexed Channel with Static Frames ........................................................... 15-9
15.4.2 One Multiplexed Channel with Dynamic Frames ..................................................... 15-9
15.4.3 Programming SIx RAM Entries .............................................................................. 15-10
15.4.4 SIx RAM Programming Example............................................................................ 15-14
15.4.5 Static and Dynamic Routing .................................................................................... 15-14
15.5 Serial Interface Registers ............................................................................................. 15-17
15.5.1 SI Global Mode Registers (SIxGMR) ..................................................................... 15-17
15.5.2 SI Mode Registers (SIxMR) .................................................................................... 15-17
15.5.3 SIx RAM Shadow Address Registers (SIxRSR) ..................................................... 15-23
15.5.4 SI Command Register (SIxCMDR)......................................................................... 15-24
15.5.5 SI Status Registers (SIxSTR)................................................................................... 15-25
15.6 Serial Interface IDL Interface Support ........................................................................ 15-25
15.6.1 IDL Interface Example ............................................................................................ 15-26
15.6.2 IDL Interface Programming..................................................................................... 15-29
15.7 Serial Interface GCI Support ....................................................................................... 15-30
15.7.1 SI GCI Activation/Deactivation Procedure ............................................................. 15-32
15.7.2 Serial Interface GCI Programming .......................................................................... 15-32
15.7.2.1 Normal Mode GCI Programming ........................................................................ 15-32
15.7.2.2 SCIT Programming.............................................................................................. 15-33
Chapter 16
CPM Multiplexing
16.1 Features .......................................................................................................................... 16-2
16.2 Enabling Connections to TSA or NMSI ........................................................................ 16-3
16.3 NMSI Configuration ...................................................................................................... 16-4
16.4 CMX Registers .............................................................................................................. 16-7
16.4.1 CMX UTOPIA Address Register (CMXUAR) ......................................................... 16-7
16.4.2 CMX SI1 Clock Route Register (CMXSI1CR)....................................................... 16-12