Freescale Semiconductor MPC8260 - Manual (Page 1298)

Parallel I/O Ports
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
40-20 Freescale Semiconductor
and/or CD to automatically control operation. This lets the user fully implement protocols V.24, X.21, and
X.21 bis (with the assistance of other general-purpose I/O lines).
To configure a port C pin as a CTS or CD pin that connects to the SCC/FCC and generates interrupts, these
steps should be followed:
1. Write the corresponding PPARC bit with a 1 and PSORC bit with 0.
2. Write the corresponding PDIRC bit with a zero.
3. Set the SIEXR bit (in the interrupt controller) to determine which edges cause interrupts.
4. Write the corresponding SIMR (mask register) bit with a 1 to allow interrupts to be generated to
the core.
5. The pin value can be read at any time using PDATC.
NOTE
After connecting CTS or CD to the SCC/FCC, the user must also choose the
normal operation mode in GSMR[DIAG] to enable and disable SCC/FCC
transmission and reception with these pins.
The IDMA-DREQ signals on port C can assert an external request to the CP instead of asserting an
interrupt to the core. Each line can be programmed to assert an interrupt request upon a high-to-low change
or any change as configured in SIEXR.
NOTE
Do not program the IDMAx-DREQ pins to assert external requests to the
IDMA, unless the IDMA is used. Otherwise, erratic operation occurs.