Freescale Semiconductor MPC8260 - Manual (Page 1340)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-12 Freescale Semiconductor
I–I Index
IDMR (IDMA mask registers), 19-24
IDSR (IDMA event (status) register), 19-24
IEEE 1149.1 test access port
block diagram, 13-2
boundary scan register, 13-3
instruction decoding, 13-6
instruction register, 13-5
nonscan chain operation, 13-7
overview, 13-1
restrictions, 13-7
TAP controller, 13-2
IMA, 33-1
FCC programming
registers, 33-26
features, 33-1
ATM features not supported, 33-4
impact on PowerQUICC II features, 33-4
PHY-layer devices supported, 33-3
PowerQUICC II versions supported, 33-3
references, 33-3
versions supported, 33-3
microcode architecture, 33-10
function partitioning, 33-10
plane management functions, 33-11
receive, 33-17
cell processing activation function, 33-22
cell processing task, 33-24
cell reception task, 33-17
IDCR-regulated cell processing, 33-23
on-demand cell processing, 33-22
summary, 33-21
transmit, 33-11
non-TRL operation, 33-13
transmit queue (ITC mode), 33-14
TRL operation, 33-12
user plan functions, 33-11
programming model, 33-24
APC programming, 33-56
ABR, 33-57
CBR, UBR, VBR, and UBR+, 33-57
data structure organization, 33-24
exceptions, 33-49
ICP cell reception exceptions, 33-51
interrupt queue entry, 33-50
FCC programming
IMA-specific parameters, 33-26
parameters, 33-26
GMODE, 33-26
RCELL_TMP_BASE, 33-26
TCELL_TMP_BASE, 33-26
group tables, 33-29
group receive control (IGRCNTL), 33-38
group receive state (IGRSTATE), 33-39
group receive table entry, 33-36
group transmit state (IGTSTATE), 33-31
ICP cell templates, 33-33
receive group frame size, 33-39
receive group order tables, 33-40
transmit group order table, 33-32
transmit table entry, 33-30
group transmit control (IGTCNTL), 33-31
IDCR timer programming, 33-52
FCC parameter shadow, 33-52
on-the-fly FCC parameter changes, 33-53
programming, 33-53
unavailable PowerQUICC II features, 33-52
IDCR counter algorithm, 33-55
IDCR events, 33-55
IDCR root parameters, 33-54
IDCR table entry, 33-54
IDCR_Init command, 33-54
master clock, 33-52
IMA FCC programming, 33-26
link tables, 33-41
link receive statistics table, 33-48
link receive table entry, 33-44
link receive control (ILRCNTL), 33-46
link receive state (ILRSTATE), 33-47
link transmit table entry, 33-41
ILTCNTL, 33-42
link transmit state (ILTSTATE), 33-43
transmit interrupt status (ITINTSTAT), 33-43
root table, 33-27
control (IMACNTL), 33-29
structures in external memory, 33-48
transmit queues, 33-48
delay compression buffers (DCB), 33-49
protocol overview, 33-4
IMA cells, 33-7
control cells, 33-7
filler cells, 33-10
IMA frame overview, 33-5
introduction, 33-4
root table data structures, 33-25
software interface and requirements, 33-58
initialization procedure, 33-59
software model, 33-58
software procedures, 33-62
end-to-end channel signalling, 33-74
transmit, 33-74
group start-up, 33-63
as initiator (TX), 33-64
as responder (RX), 33-65
IDCR operation, 33-73