Freescale Semiconductor MPC8260 - Manual (Page 1186)

ATM Transmission Convergence Layer
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
34-8 Freescale Semiconductor
Table 34-2 describes TCMODE fields.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field RXEN TXEN RPS TPS RC TC SBC CF URE LB TBA IMA SM CM
Reset 0000_0000_0000_0000
R/W R/W
Figure 34-5. TC Layer Mode Register (TCMODEx)
Table 34-2. TCMODEx Field Descriptions
Bits Name Description
0 RXEN TC Layer Rx enable bit. Enables the TC Layer Rx block operation:
0 TC Layer Rx operation is disabled.
1 TC Layer Rx operation is enabled.
1 TXEN TC Layer Tx enable bit. Enables the TC Layer Tx block operation:
0 TC Layer Tx operation is disabled.
1 TC Layer Tx operation is enabled.
2 RPS Rx Payload DeScrambling
0 Payload descrambling is performed on received payload data.
1 No payload descrambling is performed on received payload data.
3 TPS Tx Payload Scrambling
0 Payload scrambling is performed on transmitted payload data.
1 No payload scrambling is performed on transmitted payload data.
4 RC Rx Coset Enable
0 XOR with 0xAA is done on received HEC.
1 No XOR with 0xAA is done on received HEC.
5 TC Tx Coset Enable
0 XOR with 0xAA is done on transmitted HEC.
1 No XOR with 0xAA is done on transmitted HEC.
6 SBC Header Single Bit error Correction
0 Perform single bit error correction on the header according to HEC while in Synch mode.
1 Do not perform single bit error correction on the header.
7–8 CF Rx Idle/Unassigned Cells Filtering
00 No cell filtering is done on Rx cells.
01 Idle cell filtering is done - idle cells are discarded.
10 Unassigned cell filtering is done - unassigned cells are discarded.
11 Idle and unassigned cell filtering is done - both idle and unassigned cells are discarded.
The Header of idle cell (ITU-T I.361): b00000000_00000000_00000000_00000001
The Header of unassigned cell (ITU-T I.361): b00000000_00000000_00000000_0000xxx0
Note that physical layer cells bypass the TC layer; they are not filtered. Also note that the filter
works on the header only and ignores the HEC.
9 URE Underrun interrupt (TCER[UR]) enable. Underrun interrupt may be set when Idle cell is
generated by the TC.
0 Underrun interrupt disabled.
1 Underrun interrupt enabled.