Freescale Semiconductor MPC8260 - Manual (Page 19)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor xvii
Contents
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Number
Title
Page
Number
11.4 SDRAM Machine ........................................................................................................ 11-33
11.4.1 Supported SDRAM Configurations......................................................................... 11-35
11.4.2 SDRAM Power-On Initialization ............................................................................ 11-35
11.4.3 JEDEC-Standard SDRAM Interface Commands .................................................... 11-35
11.4.4 Page-Mode Support and Pipeline Accesses............................................................. 11-36
11.4.5 Bank Interleaving .................................................................................................... 11-37
11.4.5.1 Using BNKSEL Signals in Single-PowerQUICC II Bus Mode .......................... 11-37
11.4.5.2 SDRAM Address Multiplexing (SDAM and BSMA)......................................... 11-37
11.4.6 SDRAM Device-Specific Parameters...................................................................... 11-38
11.4.6.1 Precharge-to-Activate Interval............................................................................. 11-39
11.4.6.2 Activate to Read/Write Interval ........................................................................... 11-39
11.4.6.3 Column Address to First Data Out—CAS Latency............................................. 11-40
11.4.6.4 Last Data Out to Precharge.................................................................................. 11-41
11.4.6.5 Last Data In to Precharge—Write Recovery ....................................................... 11-41
11.4.6.6 Refresh Recovery Interval (RFRC) ..................................................................... 11-42
11.4.6.7 External Address Multiplexing Signal................................................................. 11-42
11.4.6.8 External Address and Command Buffers (BUFCMD)........................................ 11-42
11.4.7 SDRAM Interface Timing ....................................................................................... 11-43
11.4.8 SDRAM Read/Write Transactions........................................................................... 11-46
11.4.9 SDRAM Mode-Set Command Timing .................................................................... 11-47
11.4.10 SDRAM Refresh...................................................................................................... 11-47
11.4.11 SDRAM Refresh Timing ......................................................................................... 11-48
11.4.12 SDRAM Configuration Examples ........................................................................... 11-48
11.4.12.1 SDRAM Configuration Example (Page-Based Interleaving).............................. 11-49
11.4.13 SDRAM Configuration Example (Bank-Based Interleaving) ................................. 11-50
11.5 General-Purpose Chip-Select Machine (GPCM)......................................................... 11-51
11.5.1 Timing Configuration .............................................................................................. 11-53
11.5.1.1 Chip-Select Assertion Timing ............................................................................. 11-53
11.5.1.2 Chip-Select and Write Enable Deassertion Timing ............................................. 11-54
11.5.1.3 Relaxed Timing.................................................................................................... 11-56
11.5.1.4 Output Enable (OE) Timing ................................................................................ 11-58
11.5.1.5 Programmable Wait State Configuration ............................................................. 11-58
11.5.1.6 Extended Hold Time on Read Accesses .............................................................. 11-59
11.5.2 External Access Termination ................................................................................... 11-61
11.5.3 Boot Chip-Select Operation..................................................................................... 11-62
11.5.4 Differences between MPC8xx’s GPCM and MPC82xx’s GPCM........................... 11-63
11.6 User-Programmable Machines (UPMs)....................................................................... 11-63
11.6.1 Requests ................................................................................................................... 11-64
11.6.1.1 Memory Access Requests.................................................................................... 11-66
11.6.1.2 UPM Refresh Timer Requests ............................................................................. 11-66
11.6.1.3 Software Requests—run Command .................................................................... 11-67