Freescale Semiconductor MPC8260 - Manual (Page 20)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
xviii Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
11.6.1.4 Exception Requests.............................................................................................. 11-67
11.6.2 Programming the UPMs .......................................................................................... 11-67
11.6.3 Clock Timing ........................................................................................................... 11-67
11.6.4 The RAM Array....................................................................................................... 11-69
11.6.4.1 RAM Words ......................................................................................................... 11-70
11.6.4.1.1 Chip-Select Signals (CxTx)............................................................................. 11-74
11.6.4.1.2 Byte-Select Signals (BxTx) ............................................................................. 11-75
11.6.4.1.3 General-Purpose Signals (GxTx, GOx)........................................................... 11-76
11.6.4.1.4 Loop Control.................................................................................................... 11-76
11.6.4.1.5 Repeat Execution of Current RAM Word (REDO) ........................................ 11-76
11.6.4.2 Address Multiplexing .......................................................................................... 11-77
11.6.4.3 Data Valid and Data Sample Control................................................................... 11-77
11.6.4.4 Signals Negation.................................................................................................. 11-78
11.6.4.5 The Wait Mechanism ........................................................................................... 11-78
11.6.4.6 Extended Hold Time on Read Accesses ............................................................. 11-79
11.6.5 UPM DRAM Configuration Example ..................................................................... 11-79
11.6.6 Differences between MPC8xx UPM and MPC82xx UPM ..................................... 11-80
11.7 Memory System Interface Example Using UPM ........................................................ 11-81
11.7.0.1 EDO Interface Example....................................................................................... 11-92
11.8 Handling Devices with Slow or Variable Access Times............................................ 11-101
11.8.1 Hierarchical Bus Interface Example ...................................................................... 11-101
11.8.2 Slow Devices Example .......................................................................................... 11-101
11.9 External Master Support (60x-Compatible Mode) .................................................... 11-101
11.9.1 60x-Compatible External Masters (non-PowerQUICC II).................................... 11-102
11.9.2 PowerQUICC II External Masters ......................................................................... 11-102
11.9.3 Extended Controls in 60x-Compatible Mode ........................................................ 11-102
11.9.4 Address Incrementing for External Bursting Masters ........................................... 11-102
11.9.5 External Masters Timing........................................................................................ 11-103
11.9.5.1 Example of External Master Using the SDRAM Machine ............................... 11-105
Chapter 12
Secondary (L2) Cache Support
12.1 L2 Cache Configurations ............................................................................................... 12-1
12.1.1 Copy-Back Mode ....................................................................................................... 12-1
12.1.2 Write-Through Mode ................................................................................................. 12-2
12.1.3 ECC/Parity Mode....................................................................................................... 12-4
12.2 L2 Cache Interface Parameters ...................................................................................... 12-6
12.3 System Requirements When Using the L2 Cache Interface.......................................... 12-7
12.4 L2 Cache Operation ....................................................................................................... 12-7
12.5 Timing Example............................................................................................................. 12-7