Freescale Semiconductor MPC8260 - Manual (Page 688)

Serial Communications Controllers (SCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
20-10 Freescale Semiconductor
20.1.4 Transmit-on-Demand Register (TODR)
In normal operation, if no frame is being sent by an SCC, the CP periodically polls the R bit of the next
TxBD to see if a new frame/buffer is requested. Depending on the SCC configuration, this polling occurs
every 8–32 serial Tx clocks. The transmit-on-demand option, selected in the transmit-on-demand register
(TODR) shown in
Figure 20-5 , shortens the latency of the Tx buffer/frame and is useful in LAN-type
protocols where maximum inter-frame gap times are limited by the protocol specification.
The CP can be configured to begin processing a new frame/buffer without waiting the normal polling time
by setting TODR[TOD] after TxBD[R] is set. Because this feature favors the specified TxBD, it may affect
servicing of other SCC FIFOs. Therefore, transmitting on demand should only be used when a
high-priority TxBD has been prepared and enough time has passed since the last transmission.
Table 20-3
describes TODR fields.
20.2 SCC Buffer Descriptors (BDs)
Data associated with each SCC channel is stored in buffers and each buffer is referenced by a buffer
descriptor (BD) that can reside anywhere in dual-port RAM. The total number of 8-byte BDs is limited
only by the size of the dual-port RAM (128 BDs/1 Kbyte). These BDs are shared among all serial
controllers—SCCs, SMCs, SPI, and I
2 C. The user defines how the BDs are allocated among the
controllers.
Each 64-bit BD has the following structure:
• The half word at offset + 0x0 contains status and control bits that control and report on the data
transfer. These bits vary from protocol to protocol. The CPM updates the status bits after the buffer
is sent or received.
• The half word at offset + 0x2 (data length) holds the number of bytes sent or received.
0 15
Field TOD —
Reset 0000_0000_0000_0000
R/W W
Addr 0x0x11A0C (TODR1); 0x0x11A2C (TODR2); 0x0x11A4C (TODR3); 0x0x11A6C (TODR4)
Figure 20-5. Transmit-on-Demand Register (TODR)
Table 20-3. TODR Field Descriptions
Bits Name Description
0 TOD Transmit on demand.
0 Normal operation.
1 The CP gives high priority to the current TxBD and begins sending the frame without waiting the
normal polling time to check the TxBD’s R bit. TOD is cleared automatically after one serial clock,
but transmitting on demand continues until an unprepared (R = 0) BD is reached. TOD does not
need to be set again if new TxBDs are added to the BD table as long as older TxBDs are still
being processed. New TxBDs are processed in order. The first bit of the frame is typically clocked
out 5-6 bit times after TOD is set.
1–15 — Reserved, should be cleared.