Freescale Semiconductor ColdFire MCF52210 User Manual

Integrated microcontroller reference manual

MCF52211 ColdFire

Integrated

Microcontroller Reference Manual

Devices Supported:

MCF52210
MCF52211
MCF52212
MCF52213

Document Number: MCF52211RM

Rev. 2

09/2007

This manual is related to the following products:

ColdFire MCF52211 ColdFire MCF52213 ColdFire MCF52212

Table of contents

Document Outline

Chapter 1 Overview
- 1.1 MCF52211 Family Configurations
- 1.2 Block Diagram
- 1.3 Part Numbers and Packaging
- 1.2 Features
Chapter 2 Signal Descriptions
- 2.1 Introduction
- 2.2 Overview
- 2.3 Pin Functions
- 2.4 Reset Signals
- 2.5 PLL and Clock Signals
- 2.6 Mode Selection
- 2.7 External Interrupt Signals
- 2.8 Queued Serial Peripheral Interface (QSPI)
- 2.9 I2C I/O Signals
- 2.10 UART Module Signals
- 2.11 DMA Timer Signals
- 2.12 ADC Signals
- 2.13 General Purpose Timer Signals
- 2.14 Pulse-Width Modulator Signals
- 2.15 Debug Support Signals
- 2.16 EzPort Signal Descriptions
- 2.17 Power and Ground Pins
Chapter 3 ColdFire Core
- 3.1 Introduction
  - 3.1.1 Overview
- 3.2 Memory Map/Register Description
- 3.3 Functional Description
Chapter 4 Multiply-Accumulate Unit (MAC)
- 4.1 Introduction
  - 4.1.1 Overview
- 4.2 Memory Map/Register Definition
- 4.3 Functional Description
Chapter 5 Static RAM (SRAM)
- 5.1 Introduction
  - 5.1.1 Overview
  - 5.1.2 Features
- 5.2 Memory Map/Register Description
  - 5.2.1 SRAM Base Address Register (RAMBAR)
- 5.3 Initialization/Application Information
  - 5.3.1 SRAM Initialization Code
  - 5.3.2 Power Management
Chapter 6 Clock Module
- 6.1 Introduction
- 6.2 Features
- 6.3 Modes of Operation
- 6.4 Low-Power Mode Operation
- 6.5 Block Diagram
- 6.6 Signal Descriptions
- 6.7 Memory Map and Registers
  - 6.7.1 Register Descriptions
- 6.8 Functional Description
Chapter 7 Backup Watchdog Timer (BWT) Module
- 7.1 Introduction
  - 7.1.1 Overview
  - 7.1.2 Modes of Operation
- 7.2 Memory Map and Register Definition
  - 7.2.1 Memory Map
  - 7.2.2 Register Descriptions
- 7.3 Functional Description
Chapter 8 Power Management
- 8.1 Introduction
  - 8.1.1 Features
- 8.2 Memory Map/Register Definition
- 8.3 IPS Bus Timeout Monitor
- 8.4 Functional Description
Chapter 9 Chip Configuration Module (CCM)
- 9.1 Introduction
  - 9.1.1 Features
- 9.2 External Signal Descriptions
- 9.3 Memory Map/Register Definition
Chapter 10 Reset Controller Module
- 10.1 Introduction
- 10.2 Features
- 10.3 Block Diagram
- 10.4 Signals
  - 10.4.1 RSTI
  - 10.4.2 RSTO
- 10.5 Memory Map and Registers
  - 10.5.1 Reset Control Register (RCR)
  - 10.5.2 Reset Status Register (RSR)
- 10.6 Functional Description
Chapter 11 Real-Time Clock
- 11.1 Introduction
- 11.2 Memory Map/Register Definition
  - 11.2.1 Register Descriptions
- 11.3 Functional Description
- 11.4 Initialization/Application Information
  - 11.4.1 Flow Chart of RTC Operation
  - 11.4.2 Code Example for Initializing the Real-Time Clock
Chapter 12 System Control Module (SCM)
- 12.1 Introduction
- 12.2 Overview
- 12.3 Features
- 12.4 Memory Map and Register Definition
- 12.5 Register Descriptions
- 12.6 Internal Bus Arbitration
- 12.7 System Access Control Unit (SACU)
Chapter 13 General Purpose I/O Module
- 13.1 Introduction
- 13.2 Overview
- 13.3 Features
- 13.4 Signal Descriptions
- 13.5 Memory Map/Register Definition
  - 13.5.1 Ports Memory Map
- 13.6 Register Descriptions
- 13.7 Ports Interrupts
Chapter 14 Interrupt Controller Module
- 14.1 68K/ColdFire Interrupt Architecture Overview
  - 14.1.1 Interrupt Controller Theory of Operation
- 14.2 Memory Map
- 14.3 Register Descriptions
- 14.4 Low-Power Wakeup Operation
Chapter 15 Universal Serial Bus, OTG Capable Controller
- 15.1 Introduction
- 15.2 Functional Description
  - 15.2.1 Data Structures
- 15.3 Programmers Interface
- 15.4 Memory Map/Register Definitions
  - 15.4.1 Capability Registers
- 15.5 OTG and Host Mode Operation
- 15.6 Host Mode Operation Examples
- 15.7 On-The-Go Operation
Chapter 16 Edge Port Module (EPORT)
- 16.1 Introduction
- 16.2 Low-Power Mode Operation
- 16.3 Interrupt/GPIO Pin Descriptions
- 16.4 Memory Map/Register Definition
Chapter 17 DMA Controller Module
- 17.1 Introduction
  - 17.1.1 Overview
  - 17.1.2 Features
- 17.2 DMA Transfer Overview
- 17.3 Memory Map/Register Definition
- 17.4 Functional Description
Chapter 18 ColdFire Flash Module (CFM)
- 18.1 Introduction
  - 18.1.1 Overview
  - 18.1.2 Features
- 18.2 External Signal Description
- 18.3 Memory Map and Register Definition
- 18.4 Functional Description
Chapter 19 EzPort
- 19.1 Features
- 19.2 Modes of Operation
- 19.3 External Signal Description
  - 19.3.1 Overview
  - 19.3.2 Detailed Signal Descriptions
- 19.4 Command Definition
  - 19.4.1 Command Descriptions
- 19.5 Functional Description
- 19.6 Initialization/Application Information
Chapter 20 Programmable Interrupt Timers (PIT0-PIT1)
- 20.1 Introduction
- 20.2 Memory Map/Register Definition
- 20.3 Functional Description
Chapter 21 General Purpose Timer Module (GPT)
- 21.1 Introduction
- 21.2 Features
- 21.3 Block Diagram
- 21.4 Low-Power Mode Operation
- 21.5 Signal Description
- 21.6 Memory Map and Registers
- 21.7 Functional Description
- 21.8 Reset
- 21.9 Interrupts
Chapter 22 DMA Timers (DTIM0-DTIM3)
- 22.1 Introduction
  - 22.1.1 Overview
  - 22.1.2 Features
- 22.2 Memory Map/Register Definition
- 22.3 Functional Description
- 22.4 Initialization/Application Information
  - 22.4.1 Code Example
  - 22.4.2 Calculating Time-Out Values
Chapter 23 Queued Serial Peripheral Interface (QSPI)
- 23.1 Introduction
- 23.2 External Signal Description
- 23.3 Memory Map/Register Definition
- 23.4 Functional Description
- 23.5 Initialization/Application Information
Chapter 24 UART Modules
- 24.1 Introduction
  - 24.1.1 Overview
  - 24.1.2 Features
- 24.2 External Signal Description
- 24.3 Memory Map/Register Definition
- 24.4 Functional Description
- 24.5 Initialization/Application Information
  - 24.5.1 Interrupt and DMA Request Initialization
  - 24.5.2 UART Module Initialization Sequence
Chapter 25 I2C Interface
- 25.1 Introduction
- 25.2 Memory Map/Register Definition
- 25.3 Functional Description
- 25.4 Initialization/Application Information
Chapter 26 Analog-to-Digital Converter (ADC)
- 26.1 Introduction
- 26.2 Features
- 26.3 Block Diagram
- 26.4 Memory Map and Register Definition
- 26.5 Functional Description
Chapter 27 Pulse-Width Modulation (PWM) Module
- 27.1 Introduction
  - 27.1.1 Overview
- 27.2 Memory Map/Register Definition
- 27.3 Functional Description
  - 27.3.1 PWM Clock Select
  - 27.3.2 PWM Channel Timers
Chapter 28 Debug Module
- 28.1 Introduction
  - 28.1.1 Block Diagram
  - 28.1.2 Overview
- 28.2 Signal Descriptions
- 28.3 Real-Time Trace Support
  - 28.3.1 Begin Execution of Taken Branch (PST = 0x5)
- 28.4 Memory Map/Register Definition
- 28.5 Background Debug Mode (BDM)
- 28.6 Real-Time Debug Support
  - 28.6.1 Theory of Operation
  - 28.6.2 Concurrent BDM and Processor Operation
- 28.7 Processor Status, Debug Data Definition
  - 28.7.1 User Instruction Set
  - 28.7.2 Supervisor Instruction Set
- 28.8 Freescale-Recommended BDM Pinout
Chapter 29 IEEE 1149.1 Test Access Port (JTAG)
- 29.1 Introduction
- 29.2 External Signal Description
- 29.3 Memory Map/Register Definition
- 29.4 Functional Description
- 29.5 Initialization/Application Information
  - 29.5.1 Restrictions
  - 29.5.2 Nonscan Chain Operation
Appendix A Register Memory Map Quick Reference
Appendix B Revision History
- B.1 Changes between Rev. 1 and Rev. 2
- B.2 Changes between Rev. 0 and Rev. 1