Freescale Semiconductor MPC8260 - Manual (Page 844)

Serial Management Controllers (SMCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
27-32 Freescale Semiconductor
27.5.3 Handling the GCI C/I Channel
The C/I channel is used to control the layer 1 device. The layer 2 device in the TE sends commands and
receives indication to or from the upstream layer 1 device through C/I channel 0. In the SCIT
configuration, C/I channel 1 is used to convey real-time status information between the layer 2 device and
nonlayer 1 peripheral devices (CODECs).
27.5.3.1 SMC GCI C/I Channel Transmission Process
The core writes the data byte into the C/I TxBD and the SMC transmits the data continuously on the C/I
channel to the physical layer device.
27.5.3.2 SMC GCI C/I Channel Reception Process
The SMC receiver continuously monitors the C/I channel. When it recognizes a change in the data and this
value is received in two successive frames, it is interpreted as valid data. This is called the double last-look
method. The CP stores the received data byte in the C/I RxBD and a maskable interrupt is generated. If the
SMC is configured to support SCIT channel 1, the double last-look method is not used.
27.5.4 SMC GCI Commands
The commands in Table 27-18 are issued to the CPCR.
27.5.5 SMC GCI Monitor Channel RxBD
This BD, seen in Figure 27-15 , is used by the CP to report information about the monitor channel receive
byte.
Table 27-19 describes SMC monitor channel RxBD fields.
Table 27-18. SMC GCI Commands
Command Description
INIT TX AND
RX
PARAMETERS
Initializes transmit and receive parameters in the parameter RAM to their reset state. It is especially
useful when switching protocols on a given serial channel.
TRANSMIT
ABORT
REQUEST
This receiver command can be issued when the PowerQUICC II implements the monitor channel
protocol. When it is issued, the PowerQUICC II sends an abort request on the A bit.
TIMEOUT This transmitter command can be issued when the PowerQUICC II implements the monitor channel
protocol. It is usually issued because the device is not responding or A bit errors are detected. The
PowerQUICC II sends an abort request on the E bit at the time this command is issued.
0 1 2 3 4 7 8 15
Offset + 0 E l ER MS — DATA
Figure 27-15. SMC Monitor Channel RxBD