Freescale Semiconductor MPC8260 - Manual (Page 1185)

ATM Transmission Convergence Layer
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 34-7
The FIFO management includes emptying cells from the transmit FIFO, indicating to the UTOPIA
interface that it is full, maintaining the FIFO read and write pointers, and detecting FIFO underrun
(TCER[UR]) conditions.
34.2.3 Receive UTOPIA Interface
This block performs the receive interface with the FCC via the UTOPIA bus. It implements the UTOPIA
level-2 (multi-PHY) 8-bit PMD side (slave) interface.
34.2.4 Transmit UTOPIA Interface
This block performs the transmit interface with the FCC via the UTOPIA bus. It implements the UTOPIA
level-2 (multi-PHY) 8-bit PMD side (slave) interface.
34.3 Signals
The TC layer is operated via an SI TDM port using a serial protocol. Synchronization signals are required
for some applications and must be supported.
Table 34-1 describes the signals required for operating the
TC layer.
34.4 TC Layer Programming Mode
This section describes the TC layer-specific registers and other programming model features. For a
complete and concise list of TC layer registers, refer to
Chapter 3, “Memory Map.”
34.4.1 TC Layer Registers
Each TC layer block is controlled by registers located in the block and accessed from the 60x bus.
34.4.1.1 TC Layer Mode Register [1–8] (TCMODE x)
Each TC layer block is configured using a TC layer mode register TCMODEx, as shown in Figure 34-5 .
Table 34-1. TC Layer Signals
Signal Direction Description
Txc Input Tx clock. Clocks Tx data out of the TC to external device.
Txd Output Tx data from TC to external device.
Txsyn Input Tx synch. Synchronizes the transmit data to the beginning of a frame.
Rxc Input Rx clock. Clocks the data into the TC.
Rxd Input Rx data. From external device to the TC.
Rxsyn Input Rx synch. Synchronizes the received data.