Freescale Semiconductor MPC8260 User Manual
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MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor
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Part III, “The Hardware Interface,”
describes external signals, clocking, memory control, and
power management of the PowerQUICC II.
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Chapter 6, “External Signals,”
shows a functional pinout of the PowerQUICC II and describes
the PowerQUICC II signals.
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describes signals on the 60x bus.
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describes the operation of the bus used by processors that
implement the PowerPC architecture.
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Chapter 10, “Clocks and Power Control,”
describes the clocking architecture of the
PowerQUICC II.
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describes how the PCI bridge enables the PowerQUICC II to
gluelessly bridge PCI agents to a host processor that implements the PowerPC architecture and
how it is compliant with PCI Specification Revision 2.2.
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Chapter 11, “Memory Controller,”
describes the memory controller, which controlling a
maximum of eight memory banks shared between a general-purpose chip-select machine
(GPCM) and three user-programmable machines (UPMs).
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Chapter 12, “Secondary (L2) Cache Support,”
provides information about implementation and
configuration of a level-2 cache.
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Chapter 13, “IEEE 1149.1 Test Access Port,”
describes the dedicated user-accessible test
access port (TAP), which is fully compatible with the IEEE 1149.1 Standard Test Access Port
and Boundary Scan Architecture.
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Part IV, “Communications Processor Module,”
describes the configuration, clocking, and
operation of the various communications protocols supported by the PowerQUICC II.
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Chapter 14, “Communications Processor Module Overview,”
provides a brief overview of the
CPM.
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Chapter 15, “Serial Interface with Time-Slot Assigner,”
describes the SIU, which controls
system start-up, initialization and operation, protection, as well as the external system bus.
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Chapter 16, “CPM Multiplexing,”
describes the CPM multiplexing logic (CMX) which
connects the physical layer—UTOPIA, MII, modem lines,
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Chapter 17, “Baud-Rate Generators (BRGs),”
describes the eight independent, identical
baud-rate generators (BRGs) that can be used with the FCCs, SCCs, and SMCs.
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describes the timer implementation, which can be configured as four
identical 16-bit or two 32-bit general-purpose timers.
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Chapter 19, “SDMA Channels and IDMA Emulation,”
describes the two physical serial DMA
(SDMA) channels on the PowerQUICC II.
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Chapter 20, “Serial Communications Controllers (SCCs),”
describes the four serial
communications controllers (SCC), which can be configured independently to implement
different protocols for bridging functions, routers, and gateways, and to interface with a wide
variety of standard WANs, LANs, and proprietary networks.
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describes the PowerQUICC II implementation of universal
asynchronous receiver transmitter (UART) protocol that is used for sending low-speed data
between devices.