Freescale Semiconductor MPC8260 - Manual (Page 1323)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor Glossary-5
Interrupt. An asynchronous exception. On PowerPC processors, interrupts are a special
case of exceptions. See also asynchronous exception.
L
Latency. The time an operation requires. For example, execution latency is the number of
processor clocks an instruction takes to execute. Memory latency is the number of
bus clocks needed to perform a memory operation.
Least-significant bit (lsb). The bit of least value in an address, register, data element, or
instruction encoding.
Least-significant byte (LSB). The byte of least value in an address, register, data element,
or instruction encoding.
Little-endian. A byte-ordering method in memory where the address n of a word
corresponds to the least-significant byte. In an addressed memory word, the bytes
are ordered (left to right) 3, 2, 1, 0, with 3 being the most-significant byte.
See
Big-endian.
M
Master. The name given to a bus device that has been granted control, or mastership, of the
bus.
Memory access ordering. The specific order in which the processor performs load and
store memory accesses and the order in which those accesses complete.
Memory controller. A unit whose primary function is to control the external bus memories
and I/O devices.
Memory coherency. An aspect of caching in which it is ensured that an accurate view of
memory is provided to all devices that share system memory.
Memory consistency. Refers to agreement of levels of memory with respect to a single
processor and system memory (for example, on-chip cache, secondary cache, and
system memory).
Memory management unit (MMU). The functional unit that is capable of translating an
effective (logical) address to a physical address, providing protection
mechanisms, and defining caching methods.
Microarchitecture. The hardware details of a microprocessor’s design. Such details are
not defined by the PowerPC architecture.
Mnemonic. The abbreviated name of an instruction used for coding.
Modified state. When a cache block is in the modified state, it has been modified by the
processor since it was copied from memory. See MESI.