Freescale Semiconductor MPC8260 - Manual (Page 54)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
lii Freescale Semiconductor
Figures
Figure
Number
Title
Page
Number
14-8 Dual-Port RAM Memory Map............................................................................................ 14-19
14-9 RISC Timer Table RAM Usage .......................................................................................... 14-23
14-10 RISC Timer Command Register (TM_CMD) .................................................................... 14-24
14-11 RISC Timer Event Register (RTER)/Mask Register (RTMR)............................................ 14-25
15-1 SI Block Diagram.................................................................................................................. 15-2
15-2 Various Configurations of a Single TDM Channel ............................................................... 15-5
15-3 Dual TDM Channel Example ............................................................................................... 15-6
15-4 Enabling Connections to the TSA......................................................................................... 15-8
15-5 One TDM Channel with Static Frames and Independent Rx and Tx Routes ....................... 15-9
15-6 One TDM Channel with Shadow RAM for Dynamic Route Change................................. 15-10
15-7 SIx RAM Entry Fields ........................................................................................................ 15-10
15-8 Using the SWTR Feature .................................................................................................... 15-12
15-9 Example: SIx RAM Dynamic Changes, TDMa and b, Same SIx RAM Size .................... 15-16
15-10 SI Global Mode Registers (SIxGMR)................................................................................. 15-17
15-11 SI Mode Registers (SIxMR) ............................................................................................... 15-18
15-12 One-Clock Delay from Sync to Data (xFSD = 01)............................................................. 15-20
15-13 No Delay from Sync to Data (xFSD = 00).......................................................................... 15-20
15-14 Falling Edge (FE) Effect When CE = 1 and xFSD = 01..................................................... 15-21
15-15 Falling Edge (FE) Effect When CE = 0 and xFSD = 01..................................................... 15-21
15-16 Falling Edge (FE) Effect When CE = 1 and xFSD = 00..................................................... 15-22
15-17 Falling Edge (FE) Effect When CE = 0 and xFSD = 00..................................................... 15-23
15-18 SIx RAM Shadow Address Registers (SIxRSR) ................................................................ 15-24
15-19 SI Command Register (SIxCMDR) .................................................................................... 15-24
15-20 SI Status Registers (SIxSTR) .............................................................................................. 15-25
15-21 Dual IDL Bus Application Example ................................................................................... 15-26
15-22 IDL Terminal Adaptor......................................................................................................... 15-27
15-23 IDL Bus Signals .................................................................................................................. 15-28
15-24 GCI Bus Signals .................................................................................................................. 15-31
16-1 CPM Multiplexing Logic (CMX) Block Diagram................................................................ 16-2
16-2 Enabling Connections to the TSA......................................................................................... 16-4
16-3 Bank of Clocks ...................................................................................................................... 16-5
16-4 CMX UTOPIA Address Register (CMXUAR) .................................................................... 16-7
16-5 Connection of the Master Address........................................................................................ 16-9
16-6 Connection of the Slave Address .......................................................................................... 16-9
16-7 Multi-PHY Receive Address Multiplexing......................................................................... 16-11
16-8 CMX SI1 Clock Route Register (CMXSI1CR) .................................................................. 16-12
16-9 CMX SI2 Clock Route Register (CMXSI2CR) .................................................................. 16-13
16-10 CMX FCC Clock Route Register (CMXFCR) ................................................................... 16-14
16-11 CMX SCC Clock Route Register (CMXSCR) ................................................................... 16-16
16-12 CMX SMC Clock Route Register (CMXSMR) ................................................................. 16-19
17-1 Baud-Rate Generator (BRG) Block Diagram ....................................................................... 17-1