Freescale Semiconductor MPC8260 - Manual (Page 457)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 11-39
• Last data out to precharge (P/LSDMR[LDOTOPRE]). Section 11.4.6.4, “Last Data Out to
Precharge.”
• Write recovery, last data in to precharge (P/LSDMR[WRC]). See Section 11.4.6.5, “Last Data In
to Precharge—Write Recovery.”
• Refresh recovery interval (P/LSDMR[RFRC]). See Section 11.4.6.6, “Refresh Recovery Interval
(RFRC).”
• External address multiplexing present (P/LSDMR[EAMUX]). See Section 11.4.6.7, “External
Address Multiplexing Signal.”
• External buffers on the control lines present (P/LSDMR[BUFCMD]). See Section 11.4.6.8,
“External Address and Command Buffers (BUFCMD).”
The following sections describe the SDRAM parameters that are programmed in the P/LSDMR register.
11.4.6.1 Precharge-to-Activate Interval
As demonstrated in Figure 11-20 , this parameter, controlled by P/LSDMR[PRETOACT] defines the
earliest timing for activate or refresh command after a precharge command.
Figure 11-20. PRETOACT = 2 (2 Clock Cycles)
11.4.6.2 Activate to Read/Write Interval
As represented in Figure 11-21 , this parameter, controlled by P/LSDMR[ACTTORW], defines the earliest
timing for READ / WRITE command after an ACTIVATE command.
CLK
ALE
CS
SDRAS
SDCAS
WE
DQM
PRECHARGE
Command
ACTIVATE
MA11
MA10
MA[0–9] RAy
RAy
Bank A
Command
Bank A
PRETOACT = 2