Freescale Semiconductor MPC8260 - Manual (Page 337)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-31
9.11.1.4 PCI Outbound Base Address Registers (POBAR x)
The PCI outbound base address registers (POBARx), shown in Figure 9-18 , select the base address for the
windows which are translated to the PCI address space for transactions generated by the 60x bus master
or other local devices such as the DMA controller.
Figure 9-18. PCI Outbound Base Address Registers (POBAR x)
Table 9-5. describes POBARx.
Addresses for outbound transactions are compared to the POBARs and the IMMR register. If the
transaction does not fall within one of these two spaces, it is forwarded to the PCI bus without modification
(see
Figure 9-11 ). DMA-generated transactions to addresses which “miss” the POBARs are issued
(without translation) to the 60x bus (see Figure 9-13 ).
9.11.1.5 PCI Outbound Comparison Mask Registers (POCMR x)
The PCI outbound comparison mask registers (POCMRx), shown in Figure 9-19 , defines the window size
to translate.
Table 9-4. POTAR x Field Descriptions
Bits Name Description
31–20 — Reserved, should be cleared.
19–0 Translation Address PCI address which indicates the starting point of the outbound translated
address. The translation address must be aligned based on the window’s size.
This corresponds to bits 31-12 of a 32-bit address
31 20 19 16
Field — BA
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x1080A (POBAR0); 0x10822 (POBAR1); 0x1083A (POBAR2)
15 0
Field BA
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10808 (POBAR0); 0x10820 (POBAR1); 0x10838 (POBAR2)
Table 9-5. POBAR x Field Descriptions
Bits Name Description
31–20 — Reserved, should be cleared.
19–0 Base Address Local address which is the starting point for the outbound translation window.
This corresponds to bits 31-12 of a 32-bit address