Figure 9-39. subclass code register, Table 9-26. subclass code register description, 8 pci bus base class code register – Freescale Semiconductor MPC8260 User Manual
Page 357: Figure 9-40. pci bus base class code register, 9 pci bus cache line size register, Pci bus base class code register -51, Pci bus cache line size register -51, Subclass code register -51, Subclass code register description -51, Pci bus base class code register description -51
PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
9-51
Figure 9-39. Subclass Code Register
9.11.2.8
PCI Bus Base Class Code Register
describe the PCI bus class code register.
Figure 9-40. PCI Bus Base Class Code Register
NOTE: I
2
O Compliancy
When configured as a PCI agent device, the value of the Interface, Subclass
Code, and Base Class Code Registers are 0x01, 0x00, and 0x0E
respectively, indicating that the PowerQUICC II supports the I
2
O protocol.
The user should note that the I
2
O support is not fully standard compliant.
9.11.2.9
PCI Bus Cache Line Size Register
describe the PCI bus cache line size register.
7
0
Field
SC
Reset
0000_0000
R/W
R
Addr
0x0A
Table 9-26. Subclass Code Register Description
Bits
Name
Description
7–0
Subclass code
Identifies more specifically the function of the PCI bridge (0x00 = host bridge)
7
0
Field
BCC
Reset
Refer to
R/W
R
Addr
0x0B
Table 9-27. PCI Bus Base Class Code Register Description
Bits
Name
Description
7–0
Base class code
0x06 When the PCI bridge is configured as a host bridge to indicate “Host Bridge”.
0x0E When the PCI bridge is configured as a target device to indicate the device
is an agent and is I
2
O capable.