Freescale Semiconductor MPC8260 - Manual (Page 343)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-37
9.11.1.10 Error Mask Register (EMR)
The error mask register (EMR) register, shown in Figure 9-24 , enables the IOU to assert an interrupt or a
machine check for the various types of error conditions listed in Table 9-10 . Each mask bit is active high.
That is, if a bit value is zero, an interrupt or machine check is not asserted for the corresponding error
condition.
Figure 9-24. Error Mask Register (EMR)
Table 9-11. describes EMR fields.
3 PCI_NO_RSP PCI no response (no DEVSEL; master abort).
2 PCI_DATA_PAR_RD PCI read data parity error.
1 PCI_DATA_PAR_WR PCI write data parity error.
0 PCI_ADDR_PAR PCI address parity error (read or write).
31 16
Field —
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x1088A
15 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field —
I2O_
DBMC
NMI IRA
I2O_
IPQO
I2O_
OFQO
PERR_
WR
PERR_
RD
PCI_
SERR
TAR_
ABT
NO_
RSP
DATA_
PAR_
RD
DATA_
PAR_
WR
ADDR_
PAR
Reset 0000_1111_1111_1111
R/W R/W
Addr 0x10888
Table 9-11. EMR Field Descriptions
Bits Name Description
31–13 — Reserved, should be cleared.
12 I2O_DBMC I
2
O doorbell machine check.
0 Machine check is not enabled
1 Machine check is enabled
11 NMI General error/interrupt indication.
10 IRA Illegal register access with incorrect size.
9 I2O_IPQO I2O inbound post queue overflow.
8 I2O_OFQO I2O outbound free queue overflow.
Table 9-10. ESR Field Descriptions (continued)
Bits Name Description