Freescale Semiconductor MPC8260 User Manual
Page 541
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
IV-1
Part IV
Communications Processor Module
Intended Audience
Part IV is intended for system designers who need to implement various communications protocols on the
PowerQUICC II. It assumes a basic understanding of the PowerPC exception model, the PowerQUICC II
interrupt structure, as well as a working knowledge of the communications protocols to be used. A
complete discussion of these protocols is beyond the scope of this book.
Contents
Part IV describes behavior of the PowerQUICC II communications processor module (CPM) and the
RISC communications processor (CP) that it contains (note that this is separate from the embedded
processor that implements the PowerPC architecture).
It contains the following chapters:
•
Chapter 14, “Communications Processor Module Overview,”
provides a brief overview of the
PowerQUICC II CPM.
•
Chapter 15, “Serial Interface with Time-Slot Assigner,”
describes the SIU, which controls system
start-up, initialization and operation, protection, as well as the external system bus.
•
Chapter 16, “CPM Multiplexing,”
describes the CPM multiplexing logic (CMX) which connects
the physical layer—UTOPIA, MII, modem lines,
•
Chapter 17, “Baud-Rate Generators (BRGs),”
describes the eight independent, identical baud-rate
generators (BRGs) that can be used with the FCCs, SCCs, and SMCs.
•
describes the PowerQUICC II timer implementation, which can be
configured as four identical 16-bit or two 32-bit general-purpose timers.
•
Chapter 19, “SDMA Channels and IDMA Emulation,”
describes the two physical serial DMA
(SDMA) channels on the PowerQUICC II.
•
Chapter 20, “Serial Communications Controllers (SCCs),”
describes the four serial
communications controllers (SCC), which can be configured independently to implement different
protocols for bridging functions, routers, and gateways, and to interface with a wide variety of
standard WANs, LANs, and proprietary networks.
•
describes the PowerQUICC II implementation of universal
asynchronous receiver transmitter (UART) protocol that is used for sending low-speed data
between devices.
•
describes the PowerQUICC II implementation of HDLC
protocol.