Freescale Semiconductor MPC8260 - Manual (Page 18)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
xvi Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
10.6 PowerQUICC II Internal Clock Signals ........................................................................ 10-5
10.6.1 General System Clocks .............................................................................................. 10-5
10.7 PLL Pins ........................................................................................................................ 10-6
10.8 System Clock Control Register (SCCR)........................................................................ 10-8
10.9 System Clock Mode Register (SCMR).......................................................................... 10-9
10.10 Basic Power Structure.................................................................................................. 10-11
Chapter 11
Memory Controller
11.1 Features .......................................................................................................................... 11-3
11.2 Basic Architecture.......................................................................................................... 11-4
11.2.1 Address and Address Space Checking....................................................................... 11-7
11.2.2 Page Hit Checking ..................................................................................................... 11-7
11.2.3 Error Checking and Correction (ECC) ...................................................................... 11-8
11.2.4 Parity Generation and Checking ................................................................................ 11-8
11.2.5 Transfer Error Acknowledge (TEA) Generation ....................................................... 11-8
11.2.6 Machine Check Interrupt (MCP) Generation ............................................................ 11-8
11.2.7 Data Buffer Controls (BCTLx and LWR) ................................................................. 11-9
11.2.8 Atomic Bus Operation ............................................................................................... 11-9
11.2.9 Data Pipelining ......................................................................................................... 11-9
11.2.10 External Memory Controller Support ...................................................................... 11-10
11.2.11 External Address Latch Enable Signal (ALE) ......................................................... 11-10
11.2.12 ECC/Parity Byte Select (PBSE) .............................................................................. 11-10
11.2.13 Partial Data Valid Indication (PSDVAL) ..................................................................11-11
11.2.14 BADDR[27:31] Signal Connections ....................................................................... 11-12
11.3 Register Descriptions ................................................................................................... 11-12
11.3.1 Base Registers (BRx) ............................................................................................... 11-13
11.3.2 Option Registers (ORx) ........................................................................................... 11-15
11.3.3 60x SDRAM Mode Register (PSDMR) .................................................................. 11-20
11.3.4 Local Bus SDRAM Mode Register (LSDMR)........................................................ 11-23
11.3.5 Machine A/B/C Mode Registers (MxMR) .............................................................. 11-26
11.3.6 Memory Data Register (MDR) ................................................................................ 11-28
11.3.7 Memory Address Register (MAR) .......................................................................... 11-29
11.3.8 60x Bus-Assigned UPM Refresh Timer (PURT)..................................................... 11-30
11.3.9 Local Bus-Assigned UPM Refresh Timer (LURT) ................................................. 11-30
11.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT)................................................ 11-31
11.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT) ............................................ 11-31
11.3.12 Memory Refresh Timer Prescaler Register (MPTPR) ............................................. 11-32
11.3.13 60x Bus Error Status and Control Registers (TESCRx) .......................................... 11-33
11.3.14 Local Bus Error Status and Control Registers (L_TESCRx) .................................. 11-33