Freescale Semiconductor MPC8260 - Manual (Page 195)

System Interface Unit (SIU)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 4-23
Figure 4-17 shows SIMR_L.
Note the following:
• SCC/TC/MCC/FCC SIMR bit positions are not affected by their relative priority.
• The user can clear pending register bits that were set by multiple interrupt events only by clearing
all unmasked events in the corresponding event register.
• If an SIMR bit is masked at the same time that the corresponding SIPNR bit causes an interrupt
request to the core, the error vector is issued (if no other interrupts pending). Thus, the user should
always include an error vector routine, even if it contains only an rfi instruction. The error vector
cannot be masked.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x0x10C1C
16 17 18 19 20 21 22 23 24 28 29 30 31
Field — IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 — TMCNT PIT PCI
1
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10C1E
1 MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices
Figure 4-16. SIMR_H
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15
Field FCC1 FCC2 FCC3
1
— MCC1
2
MCC2 — SCC1 SCC2 SCC3 SCC4 TC
3
—
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x0x10C20
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field I2C SPI RTT SMC1 SMC2 IDMA1 IDMA2 IDMA3 IDMA4 SDMA — TIMER1 TIMER2 TIMER3 TIMER4 —
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10C22
1 Reserved on the MPC8255.
2
Reserved on the MPC8250 and the MPC8255.
3 MPC8264 and MPC8266 only. Reserved on all other devices.
Figure 4-17. SIMR_L