Freescale Semiconductor MPC8260 - Manual (Page 16)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
xiv Freescale Semiconductor
Contents
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Number
Title
Page
Number
9.11.2.27 PCI Configuration Register Access in Big-Endian Mode .................................... 9-62
9.11.2.27.1 Additional Information on Endianess ............................................................... 9-63
9.11.2.27.2 Notes on GPCR[LE_MODE] ........................................................................... 9-63
9.11.2.28 Initializing the PCI Configuration Registers ........................................................ 9-64
9.12 Message Unit (I2O) ...................................................................................................... 9-65
9.12.1 Message Registers...................................................................................................... 9-65
9.12.1.1 Inbound Message Registers (IMRx) ..................................................................... 9-66
9.12.1.2 Outbound Message Registers (OMRx) ................................................................. 9-66
9.12.2 Door Bell Registers ................................................................................................... 9-67
9.12.2.1 Outbound Doorbell Register (ODR) ..................................................................... 9-67
9.12.2.2 Inbound Doorbell Register (IDR) ......................................................................... 9-68
9.12.3 I
2
O Unit .................................................................................................................... 9-69
9.12.3.1 PCI Configuration Identification .......................................................................... 9-70
9.12.3.2 Inbound FIFOs ...................................................................................................... 9-70
9.12.3.2.1 Inbound Free_FIFO Head Pointer Register (IFHPR) and
Inbound Free_FIFO Tail Pointer Register (IFTPR) ..................................... 9-71
9.12.3.2.2 Inbound Post_FIFO Head Pointer Register (IPHPR) and
Inbound Post_FIFO Tail Pointer Register (IPTPR) ...................................... 9-72
9.12.3.3 Outbound FIFOs ................................................................................................... 9-74
9.12.3.3.1 Outbound Free_FIFO Head Pointer Register (OFHPR) and
Outbound Free_FIFO Tail Pointer Register (OFTPR) ................................. 9-74
9.12.3.3.2 Outbound Post_FIFO Head Pointer Register (OPHPR) and
Outbound Post_FIFO Tail Pointer Register (OPTPR) .................................. 9-75
9.12.3.4 I2O Registers ........................................................................................................ 9-77
9.12.3.4.1 Inbound FIFO Queue Port Register (IFQPR) ................................................... 9-77
9.12.3.4.2 Outbound FIFO Queue Port Register (OFQPR) ............................................... 9-78
9.12.3.4.3 Outbound Message Interrupt Status Register (OMISR) ................................... 9-78
9.12.3.4.4 Outbound Message Interrupt Mask Register (OMIMR) .................................. 9-79
9.12.3.4.5 Inbound Message Interrupt Status Register (IMISR) ....................................... 9-80
9.12.3.4.6 Inbound Message Interrupt Mask Register (IMIMR) ....................................... 9-82
9.12.3.4.7 Messaging Unit Control Register (MUCR) ...................................................... 9-83
9.12.3.4.8 Queue Base Address Register (QBAR) ............................................................ 9-84
9.13 DMA Controller............................................................................................................. 9-85
9.13.1 DMA Operation ......................................................................................................... 9-85
9.13.1.1 DMA Direct Mode................................................................................................. 9-86
9.13.1.2 DMA Chaining Mode ............................................................................................ 9-86
9.13.1.3 DMA Coherency.................................................................................................... 9-87
9.13.1.4 Halt and Error Conditions...................................................................................... 9-87
9.13.1.5 DMA Transfer Types ............................................................................................. 9-87
9.13.1.6 DMA Registers ...................................................................................................... 9-88
9.13.1.6.1 DMA Mode Register [0–3] (DMAMRx) ......................................................... 9-88