Freescale Semiconductor MPC8260 - Manual (Page 1207)

Fast Ethernet Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 35-11
35.9 Programming Model
The core configures an FCC to operate as an Ethernet controller using GFMR[MODE]. The receive errors
(collision, overrun, nonoctet-aligned frame, short frame, frame too long, and CRC error) are reported
through the RxBD. The transmit errors (underrun, heartbeat, late collision, retransmission limit, and carrier
sense lost) are reported through the TxBD.
The user should program the FDSR as described in Section 29.4, “FCC Data Synchronization Registers
(FDSRx),” with FDSR[SYN2] = 0xD5 and FDSR[SYN1] = 0x55.
35.10 Ethernet Command Set
The transmit and receive commands are issued to the CPCR; see Section 14.4, “Command Set.”
0xDC JBRC 2 Word (RMON mode only) The total number of packets received that were longer than 1518
octets (excluding framing bits but including FCS octets), and had either a bad FCS
with an integral number of octets (FCS error) or a bad FCS with a non-integral number
of octets (alignment error). Note that this definition of jabber is different than the
definition in IEEE-802.3 section 8.2.1.5 (10BASE5) and section 10.3.1.4 (10BASE2).
These documents define jabber as the condition where any packet exceeds 20 ms.
The allowed range to detect jabber is between 20 ms and 150 ms.
0xE0 P64C 2 Word (RMON mode only) The total number of packets (including bad packets) received that
were 64 octets long (excluding framing bits but including FCS octets).
0xE4 P65C 2 Word (RMON mode only) The total number of packets (including bad packets) received that
were between 65 and 127 octets long inclusive (excluding framing bits but including
FCS octets).
0xE8 P128C
2
Word (RMON mode only) The total number of packets (including bad packets) received that
were between 128 and 255 octets long inclusive (excluding framing bits but including
FCS octets).
0xEC P256C
2
Word (RMON mode only) The total number of packets (including bad packets) received that
were between 256 and 511 octets long inclusive (excluding framing bits but including
FCS octets).
0xF0 P512C 2 Word (RMON mode only) The total number of packets (including bad packets) received that
were between 512 and 1023 octets long inclusive (excluding framing bits but including
FCS octets).
0xF4 P1024C
2
Word (RMON mode only) The total number of packets (including bad packets) received that
were between 1024 and 1518 octets long inclusive (excluding framing bits but
including FCS octets).
0xF8 CAM_BUF Word Internal buffer for CAM result
0xFC — Word Reserved, should be cleared.
1
Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 14.5.2, “Parameter RAM .”
2 32-bit (modulo 232) counters maintained by the CP; cleared by the user while the channel is disabled.
Table 35-2. Ethernet-Specific Parameter RAM (continued)
Offset
1
Name Width Description