Freescale Semiconductor MPC8260 - Manual (Page 1228)

FCC HDLC Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
36-4 Freescale Semiconductor
Figure 36-2 shows an example of using HMASK and HADDR[1–4].
0x4E CRCEC 2 Hword CRC error counter. Counts frames not addressed to the user or frames received in
the BSY condition, but does not include overrun, CD lost, or abort errors.
0x50 ABTSC 2 Hword Abort sequence counter
0x52 NMARC 2 Hword Nonmatching address Rx counter. Counts nonmatching addresses received
(error-free frames only). See the HMASK and HADDR[1–4] parameter description.
0x54 MAX_CNT Word Max_length counter. Temporary decrementing counter that tracks frame length.
0x58 MFLR Hword Max frame length register. If the HDLC controller detects an incoming HDLC frame
that exceeds the user-defined value in MFLR, the rest of the frame is discarded and
the LG (Rx frame too long) bit is set in the last BD belonging to that frame. The HDLC
controller waits for the end of the frame and then reports the frame status and length
in the last RxBD. MFLR includes all in-frame bytes between the opening and closing
flags (address, control, data, and CRC).
0x5A RFTHR Hword Received frames threshold. Used to reduce the interrupt overhead that might
otherwise occur when a series of short HDLC frames arrives, each causing an RXF
interrupt. By programming RFTHR, the user lowers the frequency of RXF interrupts,
which occur only when the RFTHR value is reached. Note that the user should
provide enough empty RxBDs to receive the number of frames specified in RFTHR.
0x5C RFCNT Hword Received frames count. A decrementing counter used to implement this feature.
Initialize this counter with RFTHR.
0x5E HMASK Hword HMASK and HADDR[1–4]. The HDLC controller reads the frame address from the
HDLC receiver, checks it against the four address register values, and masks the
result with HMASK. In HMASK, a 1 represents a bit position for which address
comparison should occur; 0 represents a masked bit position. When addresses
match, the address and subsequent data are written into the buffers. When
addresses do not match and the frame is error-free, the nonmatching address
received counter (NMARC) is incremented.
Note that for 8-bit addresses, mask out (clear) the eight high-order bits in HMASK.
The eight low-order bits and HADDRx should contain the address byte that
immediately follows the opening flag. For example, to recognize a frame that begins
0x7E (flag), 0x68, 0xAA, using 16-bit address recognition, HADDRx should contain
0xAA68 and HMASK should contain 0xFFFF. See
Figure 36-2 .
0x60 HADDR1 Hword
0x62 HADDR2 Hword
0x64 HADDR3 Hword
0x66 HADDR4 Hword
0x68 TS_TMP Hword Temporary storage
0x6A TMP_MB Hword Temporary storage
1
Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 14.5.2, “Parameter RAM .”
2 DISFC, CRCEC, ABTSC, and NMARC—These 16-bit (modulo 216) counters are maintained by the CP. The user can
initialize them while the channel is disabled.
Table 36-1. FCC HDLC-Specific Parameter RAM Memory Map (continued)
Offset
1
Name Width Description