Freescale Semiconductor MPC8260 - Manual (Page 8)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
vi Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
1.7.2.5 PCI with 155-Mbps ATM ...................................................................................... 1-22
1.7.2.6 PowerQUICC II as PCI Agent............................................................................... 1-23
Chapter 2
G2 Core
2.1 Overview.......................................................................................................................... 2-1
2.2 G2 Processor Core Features ............................................................................................ 2-3
2.2.1 Instruction Unit ............................................................................................................ 2-5
2.2.2 Instruction Queue and Dispatch Unit........................................................................... 2-5
2.2.3 Branch Processing Unit (BPU) .................................................................................... 2-5
2.2.4 Independent Execution Units....................................................................................... 2-6
2.2.4.1 Integer Unit (IU) ...................................................................................................... 2-6
2.2.4.2 Floating-Point Unit (FPU) ....................................................................................... 2-6
2.2.4.3 Load/Store Unit (LSU) ............................................................................................ 2-6
2.2.4.4 System Register Unit (SRU).................................................................................... 2-7
2.2.5 Completion Unit .......................................................................................................... 2-7
2.2.6 Memory Subsystem Support........................................................................................ 2-7
2.2.6.1 Memory Management Units (MMUs)..................................................................... 2-7
2.2.6.2 Cache Units.............................................................................................................. 2-8
2.3 Programming Model ........................................................................................................ 2-8
2.3.1 Register Set .................................................................................................................. 2-8
2.3.1.1 PowerPC Register Set.............................................................................................. 2-9
2.3.1.2 PowerQUICC II-Specific Registers....................................................................... 2-11
2.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0) ................................ 2-11
2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1) ................................ 2-14
2.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2) ................................ 2-14
2.3.1.2.4 Processor Version Register (PVR)..................................................................... 2-15
2.3.2 PowerPC Instruction Set and Addressing Modes ...................................................... 2-15
2.3.2.1 Calculating Effective Addresses ............................................................................ 2-15
2.3.2.2 PowerPC Instruction Set........................................................................................ 2-16
2.3.2.3 PowerQUICC II Implementation-Specific Instruction Set.................................... 2-17
2.4 Cache Implementation ................................................................................................... 2-17
2.4.1 PowerPC Cache Model.............................................................................................. 2-18
2.4.2 PowerQUICC II Implementation-Specific Cache Implementation ........................... 2-18
2.4.2.1 Data Cache............................................................................................................. 2-18
2.4.2.2 Instruction Cache ................................................................................................... 2-20
2.4.2.3 Cache Locking ....................................................................................................... 2-20
2.4.2.3.1 Entire Cache Locking ........................................................................................ 2-20
2.4.2.3.2 Way Locking...................................................................................................... 2-20
2.5 Exception Model............................................................................................................ 2-21