Freescale Semiconductor MPC8260 - Manual (Page 69)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor lxvii
Tables
Table
Number
Title
Page
Number
11-21 SDRAM Address Multiplexing (A16–A31) ....................................................................... 11-38
11-22 60x Address Bus Partition................................................................................................... 11-49
11-23 SDRAM Device Address Port during activate Command.................................................. 11-49
11-24 SDRAM Device Address Port during read/write Command .............................................. 11-49
11-25 Register Settings (Page-Based Interleaving)....................................................................... 11-50
11-26 60x Address Bus Partition................................................................................................... 11-50
11-27 SDRAM Device Address Port during activate Command.................................................. 11-51
11-28 SDRAM Device Address Port during read/write Command .............................................. 11-51
11-29 Register Settings (Bank-Based Interleaving) ...................................................................... 11-51
11-30 GPCM Interfaces Signals.................................................................................................... 11-52
11-31 GPCM Strobe Signal Behavior ........................................................................................... 11-53
11-32 TRLX and EHTR Combinations......................................................................................... 11-59
11-33 . Boot Bank Field Values after Reset .................................................................................. 11-62
11-34 UPM Interfaces Signals ...................................................................................................... 11-63
11-35 UPM Routines Start Addresses ........................................................................................... 11-65
11-36 RAM Word Bit Settings ...................................................................................................... 11-71
11-37 MxMR Loop Field Usage ................................................................................................... 11-76
11-38 UPM Address Multiplexing ................................................................................................ 11-77
11-39 60x Address Bus Partition.................................................................................................. 11-80
11-40 DRAM Device Address Port during an activate command ................................................ 11-80
11-41 Register Settings ................................................................................................................. 11-80
11-42 UPMs Attributes Example .................................................................................................. 11-82
11-43 UPMs Attributes Example .................................................................................................. 11-89
11-44 EDO Connection Field Value Example .............................................................................. 11-92
13-1 TAP Signals........................................................................................................................... 13-2
13-2 Instruction Decoding............................................................................................................. 13-6
14-1 Possible PowerQUICC II Applications................................................................................. 14-4
14-2 Peripheral Prioritization ........................................................................................................ 14-7
14-3 RISC Controller Configuration Register Field Descriptions ................................................ 14-9
14-4 RTSCR Field Descriptions.................................................................................................. 14-11
14-5 RISC Microcode Revision Number .................................................................................... 14-12
14-6 CP Command Register Field Descriptions ......................................................................... 14-13
14-7 CP Command Opcodes ....................................................................................................... 14-15
14-8 Command Descriptions....................................................................................................... 14-16
14-9 Buffer Descriptor Format.................................................................................................... 14-20
14-10 Parameter RAM .................................................................................................................. 14-21
14-11 RISC Timer Table Parameter RAM .................................................................................... 14-23
14-12 TM_CMD Field Descriptions ............................................................................................. 14-24
15-1 SIx RAM Entry (MCC = 0) ................................................................................................ 15-11
15-2 SIx RAM Entry (MCC = 1) ................................................................................................ 15-13
15-3 SIx RAM Entry Descriptions .............................................................................................. 15-14