10 60x bus-assigned sdram refresh timer (psrt), 11 local bus-assigned sdram refresh timer (lsrt), 60x bus-assigned sdram refresh timer (psrt) -31 – Freescale Semiconductor MPC8260 User Manual
Page 449: Local bus-assigned sdram refresh timer (lsrt) -31, Local bus-assigned upm refresh timer (lurt) -31, Section 11.3.10, “60x bus-assigned sdram, Refresh timer (psrt), Lsrt), Table 11-14

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
11-31
11.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
The 60x bus assigned SDRAM refresh timer register (PSRT) is shown in
11.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT)
The local bus-assigned SDRAM refresh timer register (LSRT) is shown in
Table 11-14. Local Bus-Assigned UPM Refresh Timer (LURT)
Bits
Name Description
0–7
LURT
Refresh timer period. Determines the timer period according to the following equation:
This timer generates a refresh request for all valid banks that selected a UPM machine assigned to
the local bus (M
x
MR[BSEL] =1) and is refresh-enabled (M
x
MR[RFEN] =1). Each time the timer
expires, a qualified bank generates a refresh request using the selected UPM. The qualified banks
are rotating their requests.
Example: For a 25-MHz system clock and a required service rate of 15.6 µs, given
MPTPR[PTP] = 31, the LURT value should be 11 decimal. (12*32)/25 MHz = 15.36 µs, which is less
than the required service period of 15.6 µs.
0
7
Field
PSRT
Reset
0000_0000
R/W
R/W
Addr
Figure 11-16. 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
Table 11-15. 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
Bits
Name
Description
0–7
PSRT
Refresh timer period. Determines the timer period according to the following equation:
This timer generates refresh requests for all valid banks that selected a SDRAM machine assigned
to the 60x bus and is refresh-enabled (PSDMR[RFEN] = 1). Each time the timer expires, all banks
that qualify generate a bank staggering auto refresh request using the SDRAM machine. See
Section 11.4.10, “SDRAM Refresh
.”
Example: For a 25-MHz system clock and a required service rate of 15.6 µs, given
MPTPR[PTP] = 31, the PSRT value should be 11decimal. (12*32)/25 MHz = 15.36 µs, which is less
than the required service period of 15.6 µs.
TimerP eriod
LURT
1
+
(
)
MPTPR PTP
[
] 1
+
(
)
×
Bus Frequency
----------------------------------------------------------------------------------------
⎝
⎠
⎛
⎞
=
TimerPeriod
PSRT
1
+
(
)
MPTPR PT P
[
] 1
+
(
)
×
Bus Frequency
---------------------------------------------------------------------------------------
⎝
⎠
⎛
⎞
=