Freescale Semiconductor MPC8260 User Manual
Page 254
External Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
6-14
Freescale Semiconductor
LCL_DP[0–3]
PCI_C
/
BE[3-0]
1
Local bus data parity—Local bus data parity input/output pins. In local bus write operations the
PowerQUICC II drives these pins. In local bus read operations the accessed device drives these
pins. LCL_DP[0] is driven with a value that gives odd parity with LCL_D[0–7]. LCL_DP[1] is driven
with a value that gives odd parity with LCL_D[8–15]. LCL_DP[2] is driven with a value that gives
odd parity with LCL_D[16–23]. LCL_DP[3] is driven with a value that gives odd parity with
LCL_D[24–31].
PCI command/byte enable—PCI command/byte enable input/output pins. The PowerQUICC II
drives these pins when it is the initiator of a PCI transfer. During an address phase the
PCI_C/BE[3-0] defines the command, during the data phase PCI_C/BE[3-0] defines the byte
enables. PCI_C/BE[3] is the msb and PCI_C/BE[0] is the lsb.
IRQ0
NMI_OUT
Interrupt request 0—This input is an external line that causes an MCP interrupt to the core.
Non-maskable interrupt output—This is an output driven from PowerQUICC II’s internal interrupt
controller. Assertion of this output indicates that a non-maskable interrupt is pending in
PowerQUICC II’s internal interrupt controller.
IRQ7
INT_OUT
APE
Interrupt request 7—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
Interrupt output—This is an output driven from PowerQUICC II’s internal interrupt controller.
Assertion of this output indicates that an unmasked interrupt is pending in PowerQUICC II’s
internal interrupt controller.
Address parity error—This output pin is asserted when the PowerQUICC II detects wrong parity
driven on its address parity pins by an external master.
TRST
Test reset (JTAG)— Input only. This is the reset input to PowerQUICC II’s JTAG/COP controller.
See
and
Section 13.6, “Nonscan Chain Operation.”
TCK
Test clock (JTAG)—Input only. Provides the clock input for PowerQUICC II’s JTAG/COP controller.
TMS
Test mode select (JTAG)—Input only. Controls the state of PowerQUICC II’s JTAG/COP
controller.
TDI
Test data in (JTAG)—Input only. Data input to PowerQUICC II’s JTAG/COP controller.
TDO
Test data out (JTAG)—Output only. Data output from PowerQUICC II’s JTAG/COP controller.
TRIS
Three-state—Asserting TRIS forces all other PowerQUICC II’s pins to high impedance state.
PORESET
PCI_RST
1
Power-on reset—When asserted, this input line causes the PowerQUICC II to enter power-on
reset state.
PCI reset—PCI reset input pin. When the PowerQUICC II is an agent in the PCI system,
PCI_RST is an input.
HRESET
Hard reset—This open drain line, when asserted causes the PowerQUICC II to enter hard reset
state.
SRESET
Soft reset—This open drain line, when asserted causes the PowerQUICC II to enter the soft reset
state.
QREQ
Quiescent request— Output only. Indicates that PowerQUICC II’s internal core is about to enter
its low power mode. In the PowerQUICC II this pin will be typically used for debug purposes.
Table 6-1. External Signals (continued)
Signal Description