Freescale Semiconductor MPC8260 - Manual (Page 1168)

Inverse Multiplexing for ATM (IMA)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
33-66 Freescale Semiconductor
2. Assign corresponding group number for the new link: ILRCNTL[IGNUM] = x.
3. Assign channel number for ICP cell reception: RICPCH = x.
4. Enable desired interrupts: IRINTMSK = x
5. Allow for the reception of ICP cells during the IFSM stage: ILRCNTL[MON_ICP] = 1.
6. Indicate that this link has not yet been assigned to a group: ILRCNTL[GA] = 0.
7. Configure this link/PHY as an IMA link in the IMA Root Table by setting the corresponding bit in
IMAPHY. See Table 33-3 .
8. Enable the corresponding link/PHY in the IMA Root Table by setting the corresponding bit in
RXPHYEN. See Table 33-3 .
9. Software receives and accepts ICP cell values (e.g. M, LID, etc.).
10. Program expected LID: ILID = x
11. Program the expected ICP offset: LICPOS = x
12. Initialize the DCB pointers accordingly: DCBEP, DCBSP, DCBFP. Note, it is recommended that
the DCB be initialized to zero.
13. Configure link to “Loss of IMA Frame” state: ILRSTATE[FSES] = 2.
14. Start the IMA Frame Synchronization Mechanism (IFSM) by assigning this link to the group:
ILRCNTL[GA] = 1.
15. Software must now wait for the IFSW (IMA Frame Synchronization Working) event/exception.
16. Now that we have a “frame” synchronized link, we can proceed to allow the link to be “delay”
synchronized. Indicate that this is a new link (GDS/reconstruction function) by inverting the
current “add-new” bit value: ILRCNTL[ADD_NEW] = x.
17. Formulate new group order table with the new link included (see Section 33.4.4.2.4, “Receive
Group Order Tables” ).
18. Use the new group order table by inverting the current GOTP value: IGRCNTL[GOTP] = x.
19. The “Stall Threshold” needs to be recalculated. This parameter defines the acceptable tolerance to
an emptied DCB condition (stalled link, see LS exception). The recommended new value is:
STALL_THR = 2 x RNUMLINKS x (3 + RX_FIFO). See
Section 33.4.4.2, “IMA Group Receive
Table Entry” : IGRTE[STALL_THR] = x.
20. Start the delay compensation process for this link (in IMA Root Table) by setting the corresponding
bit in REF_LINK. See Table 33-3 .
21. Software must now wait for the link delay synchronization process to complete. A LDS (Link
Delay Synchronized) exception will be generated by the PowerQUICC II as soon as this happens.
22. It is now safe for the link to receive data, set link to “active” mode: ILRCNTL[RXSC] = 1.
33.5.4.4.2 TX Parameters
1. Reset all TX parameters in the new link table entry to zero.
2. Assign corresponding group number for the new link: ILTCNTL[IGNUM] = x.
3. Enable desired interrupts: ITINTMSK = x.
4. Software formats content of ICP template accordingly (see section “Transmit ICP Cell
Signalling”).