13 aal1 ces exceptions, 1 aal1 ces interrupt queue entry, Figure 31-30. aal1 ces interrupt queue entry – Freescale Semiconductor MPC8260 User Manual
Page 1057: Aal1 ces exceptions -41, Aal1 ces interrupt queue entry -41, Section 31.13, “aal1 ces exceptions
ATM AAL1 Circuit Emulation Service
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
31-41
31.13 AAL1 CES Exceptions
There are four circular interrupt queues available for each channel. The interrupt queue number is
programmed in RCT[INTQ] and TCT[INTQ]. Events can be masked by clearing interrupt mask bits in the
RCT and TCT.
When one of the AAL1 channels generates an interrupt request, the CP writes a new entry to the table
consisting of the channel’s number and a description of the exception. The valid (V) bit is then set and
INTQ_PTR is incremented. When INTQ_PTR reaches the entry in which W is set, it returns to the first
entry of the queue. Each one-word entry provides detailed interrupt information to the host. More details
can be found in Section 29.11, “ATM Exceptions.”
31.13.1 AAL1 CES Interrupt Queue Entry
The figure below shows an interrupt queue entry.
The table below describes interrupt queue entry fields.
0x02
—
DL
The number of octets the ATM controller should transmit from this BD’s buffer. It is not
modified by the CP. The value of DL should be greater than zero.
0x04
—
TXDBPTR
Tx data buffer pointer. Points to the address of the associated buffer. The buffer may
reside in either internal or external memory. This value is not modified by the CP.
0
1
2
3
7
8
9
10
11
12
13
14
15
Offset + 0x00
V
—
W
—
SLIPE
SLIPS
CASUP
TBNR
RXF
BSY
TXB
RXB
Offset + 0x02
Channel Code (CC)
Figure 31-30. AAL1 CES Interrupt Queue Entry
Table 31-13. AAL1 CES Interrupt Queue Entry Field Descriptions
Offset Bits
Name
Description
0x00
0
V
Valid interrupt entry
0 This interrupt queue entry is free and can be use by the CP.
1 This interrupt queue entry is valid. The host should read this interrupt and clear this
bit.
1
—
—
2
W
Wrap bit. When set, this is the last interrupt circular table entry. During initialization, the
host must clear all W bits in the table except the last one, which must be set.
3–7
—
—
8
SLIPE
Slip End.Set when an AAL1 channel exits a slip state (the channel’s adaptive counter
reaches the ATM_Start threshold and the ATM channel regains its SYNC). At this
point the receiver starts to receive the incoming cells. See
Note that this interrupt can be masked with RCT[SLIPIM=0]. See
“Receive Connection Table (RCT)
.” This interrupt has an associated channel code.
Table 31-12. AAL1 CES TxBD Field Descriptions (continued)
Offset
Bits
Name
Description