Freescale Semiconductor MPC8260 - Manual (Page 91)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor I-1
Part I
Overview
Intended Audience
Part I is intended for readers who need a high-level understanding of the PowerQUICC II.
Contents
Part I provides a high-level description of the PowerQUICC II, describing general operation and listing
basic features.
• Chapter 1, “Overview,” provides a high-level description of PowerQUICC II functions and
features. It roughly follows the structure of this book, summarizing the relevant features and
providing references for the reader who needs additional information.
• Chapter 2, “G2 Core,” provides an overview of the PowerQUICC II core.
• Chapter 3, “Memory Map,” presents a table showing where PowerQUICC II registers are mapped
in memory. It includes cross references that indicate where the registers are described in detail.
Conventions
Part I uses the following notational conventions:
mnemonics Instruction mnemonics are shown in lowercase bold.
italics Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
0x0 Prefix to denote hexadecimal number
0b0 Prefix to denote binary number
rA, rB Instruction syntax used to identify a source GPR
rD Instruction syntax used to identify a destination GPR
REG[FIELD] Abbreviations or acronyms for registers or buffer descriptors are shown in
uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For
example, MSR[LE] refers to the little-endian mode enable bit in the machine state
register.
x In certain contexts, such as in a signal encoding or a bit field, indicates a don’t
care.
n Indicates an undefined numerical value