1 data bus (d[0-63])-output, Table 7-1. data bus lane assignments, 2 data bus (d[0-63])-input – Freescale Semiconductor MPC8260 User Manual
Page 269: 2 data bus parity (dp[0-7]), 1 data bus parity (dp[0-7])-output, Data bus (d[0–63])—output -13, Data bus (d[0–63])—input -13, Data bus parity (dp[0–7]) -13, Data bus parity (dp[0–7])—output -13, Data bus lane assignments -13
![1 data bus (d[0-63])-output, Table 7-1. data bus lane assignments, 2 data bus (d[0-63])-input | 2 data bus parity (dp[0-7]), 1 data bus parity (dp[0-7])-output, Data bus (d[0–63])—output -13, Data bus (d[0–63])—input -13, Data bus parity (dp[0–7]) -13, Data bus parity (dp[0–7])—output -13, Data bus lane assignments -13 | Freescale Semiconductor MPC8260 User Manual | Page 269 / 1360](/screens/111688/269.png)
1 data bus (d[0-63])-output, Table 7-1. data bus lane assignments, 2 data bus (d[0-63])-input | 2 data bus parity (dp[0-7]), 1 data bus parity (dp[0-7])-output, Data bus (d[0–63])—output -13, Data bus (d[0–63])—input -13, Data bus parity (dp[0–7]) -13, Data bus parity (dp[0–7])—output -13, Data bus lane assignments -13 | Freescale Semiconductor MPC8260 User Manual | Page 269 / 1360