2 reception errors, 1 overrun error, 2 non-octet error (dribbling bits) – Freescale Semiconductor MCF5480 User Manual
Page 985: 3 crc error, 4 frame length violation, 5 truncation, 13 mii data frame, Reception errors -55, Mii data frame -55, Section 30.4.12.2, “reception errors
Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
30-55
30.4.12.2 Reception Errors
30.4.12.2.1 Overrun Error
If the receive block has data to put into the receive FIFO and the receive FIFO is full, the FEC sets the OV
bit in the receive frame status word (RFSW). All subsequent data in the frame will be discarded and
subsequent frames may also be discarded until the receive FIFO is serviced by the DMA and space is made
available. At this point the RFSW is written into the FIFO with the OV bit set. This frame must be
discarded by the driver.
30.4.12.2.2 Non-Octet Error (Dribbling Bits)
The Ethernet controller handles up to seven dribbling bits when the receive frame terminates past a
non-octet aligned boundary. Dribbling bits are not used in the CRC calculation. If there is a CRC error,
then the frame non-octet aligned (NO) error is reported in the RFSW. If there is no CRC error, then no error
is reported.
30.4.12.2.3 CRC Error
When a CRC error occurs with no dribble bits, the FEC closes the buffer and sets the CR bit in the RFSW.
CRC checking cannot be disabled, but the CRC error can be ignored if checking is not required.
30.4.12.2.4 Frame Length Violation
When the receive frame length exceeds MAX_FL bytes the BABR interrupt will be generated, and the LG
bit in the RFSW will be set. The frame is not truncated unless the frame length exceeds 2047 bytes).
30.4.12.2.5 Truncation
When the receive frame length exceeds 2047 bytes the frame is truncated and the TR bit is set in the RFSW.
30.4.13 MII Data Frame
Ethernet/802.3 data frames transmitted across the MII have the following format:
<inter-frame><preamble><sfd><data><efd>
The inter-frame period is an unspecified amount of time during which no data activity occurs on the MII.
The de-assertion of ERXDV and ETXEN indicate the absence of data activity.
The preamble begins a frame and has a bit value of the following:
10101010 10101010 10101010 10101010 10101010 10101010 10101010
The left-most 1 represents the LSB of the byte.
The start of frame delimiter (sfd) represents the start of a frame and has the bit value, 10101011.