Freescale Semiconductor MCF5480 User Manual
Page 827
Memory Map and Registers
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
27-9
21–20
PASC
After DSPISCK delay prescaler. The PASC field selects the prescaler value for the delay between
the last edge of DSPISCK and the negation of
DSPICS. This field is only used in master mode.
00 1 clock DSPISCK to DSPICS negation prescaler
01 3 clock DSPISCK to DSPICS negation prescaler
10 5 clock DSPISCK to DSPICS negation prescaler
11 7 clock DSPISCK to DSPICS negation prescaler
19–18
PDT
Delay after transfer prescaler. The PDT field selects the prescaler value for the delay between the
negation of the
DSPICS signal at the end of a frame and the assertion of DSPICS at the beginning
of the next frame. The PDT field is only used in master mode.
00 1 clock delay between DSPICS assertions prescaler
01 3 clock delay between DSPICS assertions prescaler
10 5 clock delay between DSPICS assertions prescaler
11 7 clock delay between DSPICS assertions prescaler
17–16
PBR
Baud rate prescaler. The PBR field selects the prescaler value for the baud rate. This field is only
used in master mode. The baud rate is the frequency of the clock (DSPISCK). The system clock is
divided by the prescaler value before the baud rate selection takes place.
00 2 clock prescaler
01 3 clock prescaler
10 5 clock prescaler
11 7 clock prescaler
15–12
CSSCK
CS to SCK delay scaler. The CSSCK field selects the scaler value for the
DSPICS to DSPISCK
delay. This field is only used in master mode. The
DSPICS to DSPISCK delay is the delay between
the assertion of
DSPICS and the first edge of the DSPISCK.
lists the scaler values. The
PCS to SCK Delay is a multiple of the system clock period and it is computed according to the
following equation:
Eqn. 27-1
See
Section 27.7.3.2, “CS to SCK Delay (tCSC)
” for more details.
11–8
ASC
After SCK delay scaler. The ASC field selects the scaler value for the after DSPISCK delay. This
field is only used in master mode. The after DSPISCK delay is the delay between the last edge of
DSPISCK and the negation of
DSPICS.
lists the scaler values.The after SCK delay is a
multiple of the system clock period, and it is computed according to the following equation:
Eqn. 27-2
See
Section 27.7.3.3, “After DSPISCK Delay (tASC)
” for more details.
Table 27-5. DCTAR Field Descriptions (Continued)
Bits
Name
Description
t
CSC
1
f
sys
--------
PCSSCK CSSCK
Ч
Ч
=
t
ASC
1
f
sys
--------
PASC ASC
Ч
Ч
=