Freescale Semiconductor MCF5485 Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for MCF5485 Freescale Semiconductor
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 1032 |
| Size: | 8.48 MB |
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Document Outline
- MCF548x Reference Manual
- Table of Contents
- About This Book
- Chapter 1 Overview
- 1.1 MCF548x Family Overview
- 1.2 MCF548x Block Diagram
- 1.3 MCF548x Family Products
- 1.4 MCF548x Family Features
- 1.4.1 ColdFire V4e Core Overview
- 1.4.2 Debug Module (BDM)
- 1.4.3 JTAG
- 1.4.4 On-Chip Memories
- 1.4.5 PLL and Chip Clocking Options
- 1.4.6 Communications I/O Subsystem
- 1.4.7 DDR SDRAM Memory Controller
- 1.4.8 Peripheral Component Interconnect (PCI)
- 1.4.9 Flexible Local Bus (FlexBus)
- 1.4.10 Security Encryption Controller (SEC)
- 1.4.11 System Integration Unit (SIU)
- Chapter 2 Signal Descriptions
- 2.1 Introduction
- 2.2 MCF548x External Signals
- 2.2.1 FlexBus Signals
- 2.2.2 SDRAM Controller Signals
- 2.2.2.1 SDRAM Data Bus (SDDATA[31:0])
- 2.2.2.2 SDRAM Address Bus (SDADDR[12:0])
- 2.2.2.3 SDRAM Bank Addresses (SDBA[1:0])
- 2.2.2.4 SDRAM Row Address Strobe (RAS)
- 2.2.2.5 SDRAM Column Address Strobe (CAS)
- 2.2.2.6 SDRAM Chip Selects (SDCS[3:0])
- 2.2.2.7 SDRAM Write Data Byte Mask (SDDM[3:0])
- 2.2.2.8 SDRAM Data Strobe (SDDQS[3:0])
- 2.2.2.9 SDRAM Clock (SDCLK[1:0])
- 2.2.2.10 Inverted SDRAM Clock (SDCLK[1:0])
- 2.2.2.11 SDRAM Write Enable (SDWE)
- 2.2.2.12 SDRAM Clock Enable (SDCKE)
- 2.2.2.13 SDR SDRAM Data Strobe (SDRDQS)
- 2.2.2.14 SDRAM Reference Voltage (VREF)
- 2.2.3 PCI Controller Signals
- 2.2.3.1 PCI Address/Data Bus (PCIAD[31:0])
- 2.2.3.2 Command/Byte Enables (PCICXBE[3:0])
- 2.2.3.3 Device Select (PCIDEVSEL)
- 2.2.3.4 Frame (PCIFRM)
- 2.2.3.5 Initialization Device Select (PCIIDSEL)
- 2.2.3.6 Initiator Ready (PCIIRDY)
- 2.2.3.7 Parity (PCIPAR)
- 2.2.3.8 Parity Error (PCIPERR)
- 2.2.3.9 Reset (PCIRESET)
- 2.2.3.10 System Error (PCISERR)
- 2.2.3.11 Stop (PCISTOP)
- 2.2.3.12 Target Ready (PCITRDY)
- 2.2.3.13 External Bus Grant (PCIBG[4:1])
- 2.2.3.14 External Bus Grant/Request Output (PCIBG0/PCIREQOUT)
- 2.2.3.15 External Bus Request (PCIBR[4:0])
- 2.2.3.16 External Request/Grant Input (PCIBR0/PCIGNTIN)
- 2.2.4 Interrupt Control Signals
- 2.2.5 Clock and Reset Signals
- 2.2.6 Reset Configuration Pins
- 2.2.6.1 AD[12:8]-CLKIN to SDCLK Ratio (CLKCONFIG[4:0])
- 2.2.6.2 AD5-FlexBus Size Configuration (FBSIZE)
- 2.2.6.3 AD4-32-bit FlexBus Configuration (FBMODE)
- 2.2.6.4 AD3-Byte Enable Configuration (BECONFIG)
- 2.2.6.5 AD2-Auto Acknowledge Configuration (AACONFIG)
- 2.2.6.6 AD[1:0]-Port Size Configuration (PSCONFIG)
- 2.2.7 Ethernet Module Signals
- 2.2.7.1 Management Data (E0MDIO, E1MDIO)
- 2.2.7.2 Management Data Clock (E0MDC, E1MDC)
- 2.2.7.3 Transmit Clock (E0TXCLK, E1TXCLK)
- 2.2.7.4 Transmit Enable (E0TXEN, E1TXEN)
- 2.2.7.5 Transmit Data 0 (E0TXD0, E1TXD0)
- 2.2.7.6 Collision (E0COL, E1COL)
- 2.2.7.7 Receive Clock (E0RXCLK, E1RXCLK)
- 2.2.7.8 Receive Data Valid (E0RXDV, E1RXDV)
- 2.2.7.9 Receive Data 0 (E0RXD0, E1RXD0)
- 2.2.7.10 Carrier Receive Sense (E0CRS, E1CRS)
- 2.2.7.11 Transmit Data 1-3 (E0TXD[3:1], E1TXD[3:1])
- 2.2.7.12 Transmit Error (E0TXER, E1TXER)
- 2.2.7.13 Receive Data 1-3 (E0RXD[3:1], E1RXD[3:1])
- 2.2.7.14 Receive Error (E0RXER, E1RXER)
- 2.2.8 Universal Serial Bus (USB)
- 2.2.9 DMA Serial Peripheral Interface (DSPI) Signals
- 2.2.9.1 DSPI Synchronous Serial Data Output (DSPISOUT)
- 2.2.9.2 DSPI Synchronous Serial Data Input (DSPISIN)
- 2.2.9.3 DSPI Serial Clock (DSPISCK)
- 2.2.9.4 DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS)
- 2.2.9.5 DSPI Chip Selects (DSPICS[2:3])
- 2.2.9.6 DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS)
- 2.2.10 FlexCAN Signals
- 2.2.11 I2C I/O Signals
- 2.2.12 PSC Module Signals
- 2.2.13 DMA Controller Module Signals
- 2.2.14 Timer Module Signals
- 2.2.15 Debug Support Signals
- 2.2.15.1 Processor Clock Output (PSTCLK)
- 2.2.15.2 Processor Status Debug Data (PSTDDATA[7:0])
- 2.2.15.3 Development Serial Clock/Test Reset (DSCLK/TRST)
- 2.2.15.4 Breakpoint/Test Mode Select (BKPT/TMS)
- 2.2.15.5 Development Serial Input/Test Data Input (DSI/TDI)
- 2.2.15.6 Development Serial Output/Test Data Output (DSO/TDO)
- 2.2.15.7 Test Clock (TCK)
- 2.2.16 Test Signals
- 2.2.17 Power and Reference Pins
- 2.2.17.1 Positive Pad Supply (EVDD)
- 2.2.17.2 Positive Core Supply (IVDD)
- 2.2.17.3 Ground (VSS)
- 2.2.17.4 USB Power (USBVDD)
- 2.2.17.5 USB Oscillator Power (USB_OSCVDD)
- 2.2.17.6 USB PHY Power (USB_PHYVDD)
- 2.2.17.7 USB Oscillator Analog Power (USB_OSCAVDD)
- 2.2.17.8 USB PLL Analog Power (USB_PLLVDD)
- 2.2.17.9 SDRAM Memory Supply (SDVDD)
- 2.2.17.10 PLL Analog Power (PLLVDD)
- 2.2.17.11 PLL Analog Ground (PLLVSS)
- Part I Processor Core
- Chapter 3 ColdFire Core
- 3.1 Core Overview
- 3.2 Features
- 3.3 Programming Model
- 3.4 Data Format Summary
- 3.5 Addressing Mode Summary
- 3.6 Instruction Set Summary
- 3.7 Instruction Execution Timing
- 3.8 Exception Processing Overview
- 3.9 Precise Faults
- Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC)
- Chapter 5 Memory Management Unit (MMU)
- 5.1 Features
- 5.2 Virtual Memory Management Architecture
- 5.2.1 MMU Architecture Features
- 5.2.2 MMU Architecture Location
- 5.2.3 MMU Architecture Implementation
- 5.2.3.1 Precise Faults
- 5.2.3.2 MMU Access
- 5.2.3.3 Virtual Mode
- 5.2.3.4 Virtual Memory References
- 5.2.3.5 Instruction and Data Cache Addresses
- 5.2.3.6 Supervisor/User Stack Pointers
- 5.2.3.7 Access Error Stack Frame
- 5.2.3.8 Expanded Control Register Space
- 5.2.3.9 Changes to ACRs and CACR
- 5.2.3.10 ACR Address Improvements
- 5.2.3.11 Supervisor Protection
- 5.3 Debugging in a Virtual Environment
- 5.4 Virtual Memory Architecture Processor Support
- 5.5 MMU Definition
- 5.6 MMU Implementation
- 5.7 MMU Instructions
- Chapter 6 Floating-Point Unit (FPU)
- Chapter 7 Local Memory
- 7.1 Interactions between Local Memory Modules
- 7.2 SRAM Overview
- 7.3 SRAM Operation
- 7.4 SRAM Register Definition
- 7.5 SRAM Initialization
- 7.6 Power Management
- 7.7 Cache Overview
- 7.8 Cache Organization
- 7.9 Cache Operation
- 7.10 Cache Register Definition
- 7.11 Cache Management
- 7.12 Cache Operation Summary
- 7.13 Cache Initialization Code
- Chapter 8 Debug Support
- 8.1 Introduction
- 8.2 Signal Descriptions
- 8.3 Real-Time Trace Support
- 8.4 Memory Map/Register Definition
- 8.4.1 Revision A Shared Debug Resources
- 8.4.2 Configuration/Status Register (CSR)
- 8.4.3 PC Breakpoint ASID Control Register (PBAC)
- 8.4.4 BDM Address Attribute Register (BAAR)
- 8.4.5 Address Attribute Trigger Registers (AATR, AATR1)
- 8.4.6 Trigger Definition Register (TDR)
- 8.4.7 Program Counter Breakpoint and Mask Registers (PBRn, PBMR)
- 8.4.8 Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1)
- 8.4.9 Data Breakpoint and Mask Registers (DBR/DBR1, DBMR/DBMR1)
- 8.4.10 PC Breakpoint ASID Register (PBASID)
- 8.4.11 Extended Trigger Definition Register (XTDR)
- 8.5 Background Debug Mode (BDM)
- 8.5.1 CPU Halt
- 8.5.2 BDM Serial Interface
- 8.5.3 BDM Command Set
- 8.5.3.1 ColdFire BDM Command Format
- 8.5.3.2 Command Sequence Diagrams
- 8.5.3.3 Command Set Descriptions
- 8.5.3.3.1 Read A/D Register (rareg/rdreg)
- 8.5.3.3.2 Write A/D Register (wareg/wdreg)
- 8.5.3.3.3 Read Memory Location (read)
- 8.5.3.3.4 Write Memory Location (write)
- 8.5.3.3.5 Dump Memory Block (dump)
- 8.5.3.3.6 Fill Memory Block (fill)
- 8.5.3.3.7 Resume Execution (go)
- 8.5.3.3.8 No Operation (nop)
- 8.5.3.3.9 Synchronize PC to the PSTDDATA Lines (sync_pc)
- 8.5.3.3.10 Force Transfer Acknowledge (force_ta)
- 8.5.3.3.11 Read Control Register (rcreg)
- 8.5.3.3.12 BDM Accesses of the Stack Pointer Registers (A7: SSP and USP)
- 8.5.3.3.13 BDM Accesses of the EMAC Registers
- 8.5.3.3.14 BDM Accesses of Floating-Point Data Registers (FPn)
- 8.5.3.3.15 Write Control Register (wcreg)
- 8.5.3.3.16 Read Debug Module Register (rdmreg)
- 8.5.3.3.17 Write Debug Module Register (wdmreg)
- 8.6 Real-Time Debug Support
- 8.7 Debug C Definition of PSTDDATA Outputs
- 8.8 ColdFire Debug History
- 8.9 Freescale-Recommended BDM Pinout
- Chapter 3 ColdFire Core
- Part II System Integration Unit
- Chapter 9 System Integration Unit (SIU)
- Chapter 10 Internal Clocks and Bus Architecture
- 10.1 Introduction
- 10.2 PLL
- 10.3 XL Bus Arbiter
- 10.3.1 Features
- 10.3.2 Arbiter Functional Description
- 10.3.3 XLB Arbiter Register Descriptions
- 10.3.3.1 Arbiter Configuration Register (XARB_CFG)
- 10.3.3.2 Arbiter Version Register (XARB_VER)
- 10.3.3.3 Arbiter Status Register (XARB_SR)
- 10.3.3.4 Arbiter Interrupt Mask Register (XARB_IMR)
- 10.3.3.5 Arbiter Address Capture Register (XARB_ADRCAP)
- 10.3.3.6 Arbiter Bus Signal Capture Register (XARB_SIGCAP)
- 10.3.3.7 Arbiter Address Tenure Time Out Register (XARB_ADRTO)
- 10.3.3.8 Arbiter Data Tenure Time Out Register (XARB_DATTO)
- 10.3.3.9 Arbiter Bus Activity Time Out Register (XARB_BUSTO)
- 10.3.3.10 Arbiter Master Priority Enable Register (XARB_PRIEN)
- 10.3.3.11 Arbiter Master Priority Register (XARB_PRI)
- Chapter 11 General Purpose Timers (GPT)
- Chapter 12 Slice Timers (SLT)
- Chapter 13 Interrupt Controller
- 13.1 Introduction
- 13.2 Memory Map/Register Descriptions
- 13.2.1 Register Descriptions
- 13.2.1.1 Interrupt Pending Registers (IPRH, IPRL)
- 13.2.1.2 Interrupt Mask Register (IMRH, IMRL)
- 13.2.1.3 Interrupt Force Registers (INTFRCH, INTFRCL)
- 13.2.1.4 Interrupt Request Level Register (IRLR)
- 13.2.1.5 Interrupt Acknowledge Level and Priority Register (IACKLPR)
- 13.2.1.6 Interrupt Control Registers 1-63 (ICRn)
- 13.2.1.7 Software and Level n IACK Registers (SWIACKR, L1IACK-L7IACK)
- 13.2.1 Register Descriptions
- Chapter 14 Edge Port Module (EPORT)
- Chapter 15 GPIO
- 15.1 Introduction
- 15.2 External Pin Description
- 15.3 Memory Map/Register Definition
- 15.3.1 Register Overview
- 15.3.2 Register Descriptions
- 15.3.2.1 Port x Output Data Registers (PODR_x)
- 15.3.2.2 Port x Data Direction Registers (PDDR_x)
- 15.3.2.3 Port x Pin Data/Set Data Registers (PPDSDR_x)
- 15.3.2.4 Port x Clear Output Data Registers (PCLRR_x)
- 15.3.2.5 Port x Pin Assignment Registers (PAR_x)
- 15.3.2.6 FlexBus Chip Select Pin Assignment Register (PAR_FBCS)
- 15.3.2.7 DMA Pin Assignment Register (PAR_DMA)
- 15.3.2.8 FEC/I2C/IRQ Pin Assignment Register (PAR_FECI2CIRQ)
- 15.3.2.9 PCI Grant Pin Assignment Register (PAR_PCIBG)
- 15.3.2.10 PCI Request Pin Assignment Register (PAR_PCIBR)
- 15.3.2.11 PSC3 Pin Assignment Register (PAR_PSC3)
- 15.3.2.12 PSC2 Pin Assignment Register (PAR_PSC2)
- 15.3.2.13 PSC1 Pin Assignment Register (PAR_PSC1)
- 15.3.2.14 PSC0 Pin Assignment Register (PAR_PSC0)
- 15.3.2.15 DSPI Pin Assignment Register (PAR_DSPI)
- 15.3.2.16 General Purpose Timer Pin Assignment Register (PAR_TIMER)
- 15.4 Functional Description
- Part III On-Chip Integration
- Chapter 16 32-Kbyte System SRAM
- Chapter 17 FlexBus
- 17.1 Introduction
- 17.2 Byte Lanes
- 17.3 Address Latch
- 17.4 External Signals
- 17.5 Chip-Select Operation
- 17.6 Functional Description
- Chapter 18 SDRAM Controller (SDRAMC)
- 18.1 Introduction
- 18.2 Overview
- 18.3 External Signal Description
- 18.3.1 SDRAM Data Bus (SDDATA[31:0])
- 18.3.2 SDRAM Address Bus (SDADDR[12:0])
- 18.3.3 SDRAM Bank Addresses (SDBA[1:0])
- 18.3.4 SDRAM Row Address Strobe (RAS)
- 18.3.5 SDRAM Column Address Strobe (CAS)
- 18.3.6 SDRAM Chip Selects (SDCS[3:0])
- 18.3.7 SDRAM Write Data Byte Mask (SDDM[3:0])
- 18.3.8 SDRAM Data Strobe (SDDQS[3:0])
- 18.3.9 SDRAM Clock (SDCLK[1:0])
- 18.3.10 Inverted SDRAM Clock (SDCLK[1:0])
- 18.3.11 SDRAM Write Enable (SDWE)
- 18.3.12 SDRAM Clock Enable (SDCKE)
- 18.3.13 SDR SDRAM Data Strobe (SDRDQS)
- 18.3.14 SDRAM Memory Supply (SDVDD)
- 18.3.15 SDRAM Reference Voltage (VREF)
- 18.4 Interface Recommendations
- 18.5 SDRAM Overview
- 18.5.1 SDRAM Commands
- 18.5.2 Power-Up Initialization
- 18.6 Functional Overview
- 18.7 Memory Map/Register Definition
- 18.8 SDRAM Example
- 18.8.1 SDRAM Signal Drive Strength Settings
- 18.8.2 SDRAM Chip Select Settings
- 18.8.3 SDRAM Configuration 1 Register Settings
- 18.8.4 SDRAM Configuration 2 Register Settings
- 18.8.5 SDRAM Control Register Settings and PALL command
- 18.8.6 Set the Extended Mode Register
- 18.8.7 Set the Mode Register and Reset DLL
- 18.8.8 Issue a PALL command
- 18.8.9 Perform Two Refresh Cycles
- 18.8.10 Clear the Reset DLL Bit in the Mode Register
- 18.8.11 Enable Automatic Refresh and Lock Mode Register
- 18.8.12 Initialization Code
- Chapter 19 PCI Bus Controller
- 19.1 Introduction
- 19.2 External Signal Description
- 19.2.1 Address/Data Bus (PCIAD[31:0])
- 19.2.2 Command/Byte Enables (PCICXBE[3:0])
- 19.2.3 Device Select (PCIDEVSEL)
- 19.2.4 Frame (PCIFRAME)
- 19.2.5 Initialization Device Select (PCIIDSEL)
- 19.2.6 Initiator Ready (PCIIRDY)
- 19.2.7 Parity (PCIPAR)
- 19.2.8 PCI Clock (CLKIN)
- 19.2.9 Parity Error (PCIPERR)
- 19.2.10 Reset (PCIRESET)
- 19.2.11 System Error (PCISERR)
- 19.2.12 Stop (PCISTOP)
- 19.2.13 Target Ready (PCITRDY)
- 19.3 Memory Map/Register Definition
- 19.3.1 PCI Type 0 Configuration Registers
- 19.3.1.1 Device ID/Vendor ID Register (PCIIDR)-PCI Dword Addr 0
- 19.3.1.2 PCI Status/Command Register (PCISCR)-PCI Dword Addr 1
- 19.3.1.3 Revision ID/Class Code Register (PCICCRIR)-PCI Dword 3
- 19.3.1.4 Configuration 1 Register (PCICR1)-PCI Dword 3
- 19.3.1.5 Base Address Register 0 (PCIBAR0)-PCI Dword 4
- 19.3.1.6 Base Address Register 1 (PCIBAR1)-PCI Dword 5
- 19.3.1.7 CardBus CIS Pointer Register PCICCPR-PCI Dword A
- 19.3.1.8 Subsystem ID/Subsystem Vendor ID Registers PCISID-PCI Dword B
- 19.3.1.9 Expansion ROM Base Address PCIERBAR-PCI Dword C
- 19.3.1.10 Capabilities Pointer (Cap_Ptr) PCICPR-PCI Dword D
- 19.3.1.11 Configuration 2 Register (PCICR2)-PCI Dword F
- 19.3.2 General Control/Status Registers
- 19.3.2.1 Global Status/Control Register (PCIGSCR)
- 19.3.2.2 Target Base Address Translation Register 0 (PCITBATR0)
- 19.3.2.3 Target Base Address Translation Register 1 (PCITBATR1)
- 19.3.2.4 Target Control Register (PCITCR)
- 19.3.2.5 Initiator Window 0 Base/Translation Address Register (PCIIW0BTAR)
- 19.3.2.6 Initiator Window 1 Base/Translation Address Register (PCIIW1BTAR)
- 19.3.2.7 Initiator Window 2 Base/Translation Address Register (PCIIW2BTAR)
- 19.3.2.8 Initiator Window Configuration Register (PCIIWCR)
- 19.3.2.9 Initiator Control Register (PCIICR)
- 19.3.2.10 Initiator Status Register (PCIISR)
- 19.3.2.11 Configuration Address Register (PCICAR)
- 19.3.3 Communication Subsystem Interface Registers
- 19.3.3.1 Comm Bus FIFO Transmit Interface
- 19.3.3.1.1 Tx Packet Size Register (PCITPSR)
- 19.3.3.1.2 Tx Start Address Register (PCITSAR)
- 19.3.3.1.3 Tx Transaction Control Register (PCITTCR)
- 19.3.3.1.4 Tx Enables Register (PCITER)
- 19.3.3.1.5 Tx Next Address Register (PCITNAR)
- 19.3.3.1.6 Tx Last Word Register (PCITLWR)
- 19.3.3.1.7 Tx Done Counts Register (PCITDCR)
- 19.3.3.1.8 Tx Status Register (PCITSR)
- 19.3.3.1.9 Tx FIFO Data Register (PCITFDR)
- 19.3.3.1.10 Tx FIFO Status Register (PCITFSR)
- 19.3.3.1.11 Tx FIFO Control Register (PCITFCR)
- 19.3.3.1.12 Tx FIFO Alarm Register (PCITFAR)
- 19.3.3.1.13 Tx FIFO Read Pointer Register (PCITFRPR)
- 19.3.3.1.14 Tx FIFO Write Pointer Register (PCITFWPR)
- 19.3.3.2 Comm Bus FIFO Receive Interface
- 19.3.3.2.1 Rx Packet Size Register (PCIRPSR)
- 19.3.3.2.2 Rx Start Address Register (PCIRSAR)
- 19.3.3.2.3 Rx Transaction Control Register (PCIRTCR)
- 19.3.3.2.4 Rx Enables Register (PCIRER)
- 19.3.3.2.5 Rx Next Address Register (PCIRNAR)
- 19.3.3.2.6 Rx Done Counts Register (PCIRDCR)
- 19.3.3.2.7 Rx Status Register (PCIRSR)
- 19.3.3.2.8 Rx FIFO Data Register (PCIRFDR)
- 19.3.3.2.9 Rx FIFO Status Register (PCIRFSR)
- 19.3.3.2.10 Rx FIFO Control Register (PCIRFCR)
- 19.3.3.2.11 Rx FIFO Alarm Register (PCIRFAR)
- 19.3.3.2.12 Rx FIFO Read Pointer Register (PCIRFRPR)
- 19.3.3.2.13 Rx FIFO Write Pointer Register (PCIRFWPR)
- 19.3.3.1 Comm Bus FIFO Transmit Interface
- 19.3.1 PCI Type 0 Configuration Registers
- 19.4 Functional Description
- 19.5 Application Information
- 19.6 XL Bus Arbitration Priority
- Chapter 20 PCI Bus Arbiter Module
- Chapter 21 FlexCAN
- 21.1 Introduction
- 21.2 External Signals
- 21.3 Memory Map/Register Definition
- 21.3.1 FlexCAN Memory Map
- 21.3.2 Register Descriptions
- 21.3.2.1 FlexCAN Module Configuration Register (CANMCR)
- 21.3.2.2 FlexCAN Control Register (CANCTRL)
- 21.3.2.3 FlexCAN Timer Register (TIMER)
- 21.3.2.4 Rx Mask Registers
- 21.3.2.5 FlexCAN Error Counter Register (ERRCNT)
- 21.3.2.6 FlexCAN Error and Status Register (ERRSTAT)
- 21.3.2.7 Interrupt Mask Register (IMASK)
- 21.3.2.8 Interrupt Flag Register (IFLAG)
- 21.4 Functional Overview
- 21.5 FlexCAN Initialization Sequence
- Chapter 22 Integrated Security Engine (SEC)
- 22.1 Features
- 22.2 ColdFire Security Architecture
- 22.3 Block Diagram
- 22.4 Overview
- 22.5 Memory Map/Register Definition
- 22.6 Controller
- 22.6.1 EU Access
- 22.6.2 Multiple EU Assignment
- 22.6.3 Multiple Channels
- 22.6.4 Controller Registers
- 22.6.4.1 EU Assignment Control Registers (EUACRH and EUACRL)
- 22.6.4.2 EU Assignment Status Registers (EUASRH and EUASRL)
- 22.6.4.3 SEC Interrupt Mask Registers (SIMRH and SIMRL)
- 22.6.4.4 SEC Interrupt Status Registers (SISRH and SISRL)
- 22.6.4.5 SEC Interrupt Control Registers (SICRH and SICRL)
- 22.6.4.6 SEC ID Register (SIDR)
- 22.6.4.7 SEC Master Control Register (SMCR)
- 22.6.4.8 Master Error Address Register (MEAR)
- 22.7 Channels
- 22.8 ARC Four Execution Unit (AFEU)
- 22.9 Data Encryption Standard Execution Units (DEU)
- 22.10 Message Digest Execution Unit (MDEU)
- 22.11 RNG Execution Unit (RNG)
- 22.12 Advanced Encryption Standard Execution Units (AESU)
- 22.13 Descriptors
- 22.14 EU Specific Data Packet Descriptors
- Chapter 23 IEEE 1149.1 Test Access Port (JTAG)
- Part IV Communications Subsystem
- Chapter 24 Multichannel DMA
- 24.1 Introduction
- 24.2 External Signals
- 24.3 Memory Map/Register Definitions
- 24.3.1 DMA Task Memory
- 24.3.2 Memory Structure
- 24.3.3 DMA Registers
- 24.3.3.1 DMA Register Map
- 24.3.3.2 Task Base Address Register (TaskBAR)
- 24.3.3.3 Current Pointer (CP)
- 24.3.3.4 End Pointer (EP)
- 24.3.3.5 Variable Pointer (VP)
- 24.3.3.6 PTD Control (PTD)
- 24.3.3.7 DMA Interrupt Pending (DIPR)
- 24.3.3.8 DMA Interrupt Mask Register (DIMR)
- 24.3.3.9 Task Control Registers (TCRn)
- 24.3.3.10 Priority Registers (PRIORn)
- 24.3.3.11 Initiator Mux Control Register (IMCR)
- 24.3.3.12 Task Size Registers (TSKSZ[0:1])
- 24.3.3.13 Debug Comparator Registers (DBGCOMPn)
- 24.3.3.14 Debug Control (DBGCTL)
- 24.3.3.15 Debug Status (DBGSTAT)
- 24.3.3.16 PTD Debug Registers
- 24.3.4 External Request Module Registers
- 24.4 Functional Description
- 24.5 Programming Model
- 24.6 Timing Diagrams
- Chapter 25 Comm Timer Module (CTM)
- Chapter 26 Programmable Serial Controller (PSC)
- 26.1 Introduction
- 26.2 Signal Description
- 26.3 Memory Map/Register Definition
- 26.3.1 Overview
- 26.3.2 Module Memory Map
- 26.3.3 Register Descriptions
- 26.3.3.1 Mode Register 1(PSCMR1n)
- 26.3.3.2 Mode Register 2 (PSCMR2n)
- 26.3.3.3 Status Register (PSCSRn)
- 26.3.3.4 Clock Select Register (PSCCSRn)
- 26.3.3.5 Command Register (PSCCRn)
- 26.3.3.6 Receiver Buffer (PSCRBn) and Transmitter Buffer (PSCTBn)
- 26.3.3.7 Input Port Change Register (PSCIPCRn)
- 26.3.3.8 Auxiliary Control Register (PSCACRn)
- 26.3.3.9 Interrupt Status Register (PSCISRn)
- 26.3.3.10 Interrupt Mask Register (PSCIMRn)
- 26.3.3.11 Counter Timer Registers (PSCCTURn, PSCCTLRn)
- 26.3.3.12 Input Port (PSCIPn)
- 26.3.3.13 Output Port Bit Set (PSCOPSETn)
- 26.3.3.14 Output Port Bit Reset (PSCOPRESETn)
- 26.3.3.15 PSC/IrDA Control Register (PSCSICRn)
- 26.3.3.16 Infrared Control Register 1 (PSCIRCR1n)
- 26.3.3.17 Infrared Control Register 2 (PSCIRCR2n)
- 26.3.3.18 Infrared SIR Divide Register (PSCIRSDRn)
- 26.3.3.19 Infrared MIR Divide Register (PSCIRMDRn)
- 26.3.3.20 Infrared FIR Divide Register (PSCIRFDRn)
- 26.3.3.21 Rx and Tx FIFO Counter Register (PSCRFCNTn, PSCTFCNTn)
- 26.3.3.22 Rx and Tx FIFO Data Register (PSCRFDRn, PSCTFDRn)
- 26.3.3.23 Rx and Tx FIFO Status Register (PSCRFSRn, PSCTFSRn)
- 26.3.3.24 Rx and Tx FIFO Control Register (PSCRFCRn, PSCTFCRn)
- 26.3.3.25 Rx and Tx FIFO Alarm Register (PSCRFARn, PSCTFARn)
- 26.3.3.26 Rx and Tx FIFO Read Pointer (PSCRFRPn, PSCTFRPn)
- 26.3.3.27 Rx and Tx FIFO Write Pointer (PSCRFWPn, PSCTFWPn)
- 26.3.3.28 Rx and Tx FIFO Last Read Frame Pointer (PSCRLRFPn, PSCTLRFPn)
- 26.3.3.29 Rx and Tx FIFO Last Write Frame Pointer (PSCRLWFPn, PSCTLWFPn)
- 26.4 Functional Description
- 26.5 Resets
- 26.6 Interrupts
- 26.7 Software Environment
- Chapter 27 DMA Serial Peripheral Interface (DSPI)
- 27.1 Overview
- 27.2 Features
- 27.3 Block Diagram
- 27.4 Modes of Operation
- 27.5 Signal Description
- 27.5.1 Overview
- 27.5.2 Detailed Signal Descriptions
- 27.5.2.1 DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS)
- 27.5.2.2 DSPI Peripheral Chip Selects 2-3 (DSPICS[2:3])
- 27.5.2.3 DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS)
- 27.5.2.4 DSPI Serial Input (DSPISIN)
- 27.5.2.5 DSPI Serial Output (DSPISOUT)
- 27.5.2.6 DSPI Serial Clock (DSPISCK)
- 27.6 Memory Map and Registers
- 27.6.1 DSPI Module Configuration Register (DMCR)
- 27.6.2 DSPI Transfer Count Register (DTCR)
- 27.6.3 DSPI Clock and Transfer Attributes Registers 0-7 (DCTARn)
- 27.6.4 DSPI Status Register (DSR)
- 27.6.5 DSPI DMA/Interrupt Request Select Register (DIRSR)
- 27.6.6 DSPI Tx FIFO Register (DTFR)
- 27.6.7 DSPI Rx FIFO Register (DRFR)
- 27.6.8 DSPI Tx FIFO Debug Registers 0-3 (DTFDRn)
- 27.6.9 DSPI Rx FIFO Debug Registers 0-3 (DRFDRn)
- 27.7 Functional Description
- 27.8 Initialization and Application Information
- Chapter 28 I2C Interface
- Chapter 29 USB 2.0 Device Controller
- 29.1 Introduction
- 29.2 Memory Map/Register Definition
- 29.2.1 USB Memory Map
- 29.2.2 USB Request, Control, and Status Registers
- 29.2.2.1 USB Status Register (USBSR)
- 29.2.2.2 USB Control Register (USBCR)
- 29.2.2.3 USB Descriptor RAM Control Register (DRAMCR)
- 29.2.2.4 USB Descriptor RAM Data Register (DRAMDR)
- 29.2.2.5 USB Interrupt Status Register (USBISR)
- 29.2.2.6 USB Interrupt Mask Register (USBIMR)
- 29.2.2.7 USB Application Interrupt Status Register (USBAISR)
- 29.2.2.8 USB Application Interrupt Mask Register (USBAIMR)
- 29.2.2.9 Endpoint Info Register (EPINFO)
- 29.2.2.10 USB Configuration Value Register (CFGR)
- 29.2.2.11 USB Configuration Attribute Register (CFGAR)
- 29.2.2.12 USB Device Speed Register (SPEEDR)
- 29.2.2.13 USB Frame Number Register (FRMNUMR)
- 29.2.2.14 USB Endpoint Transaction Number Register (EPTNR)
- 29.2.2.15 USB Application Interface Update Register (IFUR)
- 29.2.2.16 USB Configuration Interface Register (IFRn)
- 29.2.3 USB Counter Registers
- 29.2.3.1 USB Packet Passed Count Register (PPCNT)
- 29.2.3.2 USB Dropped Packet Counter Register (DPCNT)
- 29.2.3.3 USB CRC Error Counter Register (CRCECNT)
- 29.2.3.4 USB Bitstuffing Error Counter Register (BSECNT)
- 29.2.3.5 USB PID Error Counter Register (PIDECNT)
- 29.2.3.6 USB Framing Error Counter Register (FRMECNT)
- 29.2.3.7 USB Transmitted Packet Counter Register (TXPCNT)
- 29.2.3.8 USB Counter Overflow Register (CNTOVR)
- 29.2.4 Endpoint Context Registers
- 29.2.4.1 Endpoint n Attribute Control Register (EP0ACR, EPnOUTACR, EPnINACR)
- 29.2.4.2 Endpoint n Max Packet Size Register (EP0MPSR, EPnOUTMPSR, EPnINMPSR)
- 29.2.4.3 Endpoint n Interface Number Register (EP0IFR, EPnOUTIFR, EPnINIFR)
- 29.2.4.4 Endpoint n Status Register (EP0SR, EPnOUTSR, EPnINSR)
- 29.2.4.5 bmRequest Type Register (BMRTR)
- 29.2.4.6 bRequest Type Register (BRTR)
- 29.2.4.7 wValue Register (WVALUER)
- 29.2.4.8 wIndex Register (WINDEXR)
- 29.2.4.9 wLength Register (WLENGTHR)
- 29.2.4.10 Endpoint n Sync Frame Register (EPnOUTSFR, EPnINSFR)
- 29.2.5 USB Endpoint FIFO Registers
- 29.2.5.1 USB Endpoint n Status and Control Register (EPnSTAT)
- 29.2.5.2 USB Endpoint n Interrupt Status Register (EPnISR)
- 29.2.5.3 USB Endpoint n Interrupt Mask Register (EPnIMR)
- 29.2.5.4 USB Endpoint n FIFO RAM Configuration Register (EPnFRCFGR)
- 29.2.5.5 USB Endpoint n FIFO Data Register (EPnFDR)
- 29.2.5.6 USB Endpoint n FIFO Status Register (EPnFSR)
- 29.2.5.7 USB Endpoint n FIFO Control Register (EPnFCR)
- 29.2.5.8 USB Endpoint n FIFO Alarm Register (EPnFAR)
- 29.2.5.9 USB Endpoint n FIFO Read Pointer (EPnFRP)
- 29.2.5.10 USB Endpoint n FIFO Write Pointer (EPnFWP)
- 29.2.5.11 USB Endpoint n Last Read Frame Pointer (EPnLRFP)
- 29.2.5.12 USB Endpoint n Last Write Frame Pointer (EPnLWFP)
- 29.3 Functional Description
- 29.4 Software Interface
- Chapter 30 Fast Ethernet Controller (FEC)
- 30.1 Introduction
- 30.2 External Signals
- 30.2.1 Transmit Clock (EnTXCLK)
- 30.2.2 Receive Clock (EnRXCLK)
- 30.2.3 Transmit Enable (EnTXEN)
- 30.2.4 Transmit Data[3:0] (EnTXD[3:0])
- 30.2.5 Transmit Error (EnTXER)
- 30.2.6 Receive Data Valid (EnRXDV)
- 30.2.7 Receive Data[3:0] (EnRXD[3:0])
- 30.2.8 Receive Error (EnRXER)
- 30.2.9 Carrier Sense (EnCRS)
- 30.2.10 Collision (EnCOL)
- 30.2.11 Management Data Clock (EnMDC)
- 30.2.12 Management Data (EnMDIO)
- 30.3 Memory Map/Register Definition
- 30.3.1 Top Level Module Memory Map
- 30.3.2 Detailed Memory Map (Control/Status Registers)
- 30.3.3 MIB Block Counters Memory Map
- 30.3.3.1 Ethernet Interrupt Event Register (EIR)
- 30.3.3.2 Interrupt Mask Register (EIMR)
- 30.3.3.3 Ethernet Control Register (ECR)
- 30.3.3.4 MII Management Frame Register (MMFR)
- 30.3.3.5 MII Speed Control Register (MSCR)
- 30.3.3.6 MIB Control Register (MIBC)
- 30.3.3.7 Receive Control Register (RCR)
- 30.3.3.8 Receive Hash Register (RHR)
- 30.3.3.9 Transmit Control Register (TCR)
- 30.3.3.10 Physical Address Low Register (PALR)
- 30.3.3.11 Physical Address High Register (PAHR)
- 30.3.3.12 Opcode/Pause Duration Register (OPD)
- 30.3.3.13 Individual Address Upper Register (IAUR)
- 30.3.3.14 Individual Address Lower Register (IALR)
- 30.3.3.15 Group Address Upper Register (GAUR)
- 30.3.3.16 Group Address Lower Register (GALR)
- 30.3.3.17 FEC Transmit FIFO Watermark Register (FECTFWR)
- 30.3.3.18 FEC Receive FIFO Data Register (FECRFDR)
- 30.3.3.19 FEC Receive FIFO Status Register (FECRFSR)
- 30.3.3.20 FEC Receive FIFO Control Register (FECRFCR)
- 30.3.3.21 FEC Receive FIFO Last Read Frame Pointer Register (FECRLRFP)
- 30.3.3.22 FEC Receive FIFO Last Write Frame Pointer Register (FECRLWFP)
- 30.3.3.23 FEC Receive FIFO Alarm Register (FECRFAR)
- 30.3.3.24 FEC Receive FIFO Read Pointer Register (FECRFRP)
- 30.3.3.25 FEC Receive FIFO Write Pointer Register (FECRFWP)
- 30.3.3.26 FEC Transmit FIFO Data Register (FECTFDR)
- 30.3.3.27 FEC Transmit FIFO Status Register (FECTFSR)
- 30.3.3.28 FEC Transmit FIFO Control Register (FECTFCR)
- 30.3.3.29 FEC Transmit FIFO Last Read Frame Pointer Register (FECTLRFP)
- 30.3.3.30 FEC Transmit FIFO Last Write Frame Pointer Register (FECTLWFP)
- 30.3.3.31 FEC Transmit FIFO Alarm Register (FECTFAR)
- 30.3.3.32 FEC Transmit FIFO Read Pointer Register (FECTFRP)
- 30.3.3.33 FEC Transmit FIFO Write Pointer Register (FECTFWP)
- 30.3.3.34 FEC FIFO Reset Register (FECFRST)
- 30.3.3.35 FEC CRC and Transmit Frame Control Word Register (FECCTCWR)
- 30.4 Functional Description
- 30.4.1 Initialization Sequence
- 30.4.2 Frame Control/Status Words
- 30.4.3 Network Interface Options
- 30.4.4 FEC Frame Transmission
- 30.4.5 FEC Frame Reception
- 30.4.6 Ethernet Address Recognition
- 30.4.7 Hash Algorithm
- 30.4.8 Full Duplex Flow Control
- 30.4.9 Inter-Packet Gap (IPG) Time
- 30.4.10 Collision Handling
- 30.4.11 Internal and External Loopback
- 30.4.12 Ethernet Error-Handling Procedure
- 30.4.13 MII Data Frame
- 30.4.14 MII Management Frame Structure
- Chapter 24 Multichannel DMA
- Part V Mechanical
- Index