Freescale Semiconductor MCF5480 - Manual (Page 120)

MCF548x Reference Manual, Rev. 3
3-16 Freescale Semiconductor
Instruction encodings disallow use of address registers for byte operands. When an address register is a
source operand, either the low-order word or the entire longword operand is used, depending on the
operation size. Word-length source operands are sign-extended to 32 bits and then used in the operation
with an address register destination. When an address register is a destination, the entire register is
affected, regardless of the operation size. Figure 3-10 shows integer formats for address registers.
The size of control registers varies according to function. Some have undefined bits reserved for future
definition by Freescale. Those bits read as zeros and must be written as zeros for future compatibility.
Operations to the SR and CCR are word-sized. The upper CCR byte is read as all zeros and is ignored when
written, regardless of privilege mode.
3.4.1.2 Integer Data Format Organization in Memory
ColdFire processors use big-endian addressing. Byte-addressable memory organization allows lower
addresses to correspond to higher-order bytes. The address N of a longword data item corresponds to the
address of the high-order word. The lower-order word is at address N + 2. The address of a word data item
corresponds to the address of the high-order byte. The lower-order byte is at address N + 1. This
organization is shown in Figure 3-11 .
31 30 1 0
msb lsb Bit (0 bit number 31)
31 8 7 6 1 0
Not used msb Lower-order byte lsb Byte (8 bits)
31 16 15 14 1 0
Not used msb Lower-order word lsb Word (16 bits)
31 30 1 0
msb Longword lsb Longword (32 bits)
Figure 3-9. Organization of Integer Data Format in Data Registers
31 16 15 0
Sign-Extended 16-Bit Address Operand
31 0
Full 32-Bit Address Operand
Figure 3-10. Organization of Integer Data Formats in Address Registers